Hardware security remains as a major concern in the circuit design ow. Logic block based encryption has been widely adopted as a simple but effective protection method. In this paper, the potential threat arising from the rapidly developing field, i.e., machine learning, is researched. To illustrate the challenge, this work presents a standard attack paradigm, in which a three-layer neural network and a naive Bayes classifier are utilized to exemplify the key-guessing attack on logic encryption. Backed with validation results obtained from both combinational and sequential benchmarks, the presented attack scheme can specifically accelerate the decryption process of partial keys, which may serve as a new perspective to reveal the potential vulnerability for current anti-attack designs.

This paper presents an improved test data compression scheme based on a combination of test data compatibility and dictionary for multi-scan designs to reduce test data volume and thus test cost. The proposed method includes two steps. First a drive bit matrix with less columns is generated by the compatibilities between the columns of the initial scan bit matrix, also the inverse compatibilities and the logic dependencies between the columns of mid bit matrixes. Secondly a dictionary bit matrix with limited rows is constructed, which has the properties that for each row of the drive bit matrix, a compatible row exists or can be generated by XOR operation of multiple rows in the dictionary bit matrix and the total number of rows used to compute all compatible rows is minimal. The rows in the dictionary matrix are encoded to further reduce the number of ATE channels and test data volume. Experimental results for the large ISCAS 89 benchmarks show that the proposed method significantly reduces test data volume for multi-scan designs.