The exponential explosive growth in transistor density enhances chip performance, while introducing significant thermal management challenges based on the Moore law. Effective thermal management is critical to maintaining chip performance and preventing damage in high-power-density systems. Conventional passive cooling, such as heat sinks and thermal interface materials, struggle to address the transient and localized heat flux in modern chips. It is thus necessary to develop innovative cooling solutions beyond conventional techniques. Thermoelectric cooling (TEC), based on the Peltier effect, stands out due to its precise temperature control, rapid thermal response, and high reliability. Furthermore, its adaptability to complex and uneven thermal profiles renders it particularly effective in managing localized hotspots in high-performance chips. However, realizing the full potential of TEC requires the development on material design, device integration as well as system-level optimization.

This review represents the foundational principles of thermoelectrics (TEs) and analyzes the theoretical formulations pertaining to maximum heat dissipation power and cooling coefficient. It highlights that chip-level TEC differs from conventional goals, prioritizing a high the dimensionless figure of merit and a low thermal conductivity. Instead, chip applications require a balance between the relatively high thermal conductivity and elevated power factor to facilitate efficient heat dissipation. This review evaluates mainstream TE materials, including bismuth telluride-based materials, selenide based-materials, and magnesium based-alloys, alongside promising emerging materials such as Heusler alloys and magnon-drag metals. Some fabrication strategies, including nanostructure design, doping, and interface engineering, are emphasized.

Except for materials, device design is critical for chip thermal management. TEC encounters commercialization challenges due to the need for ultra-thin (i.e., <50 μm) film structures directly attached to chip hotspots. Optimizing the geometric dimensions of TE legs (i.e., n-type and p-type material width ratios) and modular layouts enables efficient localized cooling, while minimizing interfacial thermal resistance and electrical losses. Devices must also handle high heat flux densities (>1000 W/cm²) and provide millisecond-scale thermal responses. Two primary micro-TEC architectures including out-of-plane and in-plane TE devices are examined. Note that multi-stage module configurations can significantly improve cooling performance via reducing cold-side temperatures and enhancing heat extraction efficiency.

For the encapsulation architectures, two-dimensional (2D) and three-dimensional (3D) architectures with system-level optimization of thin-film TECs are explored. Integrating TEC with liquid cooling or heat pipes address the constraints of single method, thus providing effective solutions for both hotspot cooling and uniform heat dissipation. For instance, TE modules can decrease the cold-end temperature in liquid cooling systems or provide localized cooling in heat pipe setups, thereby ensuring optimal thermal distribution. As chip designs increasingly trend towards higher integration and miniaturization, the scalability and compactness of TE modules become critical. Advances in nanotechnology, 3D integration, and composite materials propel the development of ultra-thin, high-power-density TE modules that seamlessly integrate into chip architectures. Innovations in cost-effective manufacturing and material reliability are also essential for advancing commercialization and long-term sustainability.

TEC technology offers precise temperature control, addressing challenges like localized hotspots and complex heat flows in high-power-density chips, which is a key technology for sustainable and high-efficiency thermal management. However, the existing researches still face significant challenges in achieving the ultra-thin designs and high-efficiency required for modern chip architectures. The ability to manage transient high heat flux while maintaining scalability and cost-efficiency remains a concern. Future efforts should focus on the balance of cost, durability, and TE properties of materials through nanoengineering, doping, and interface engineering to enhance their performance. In terms of device design, optimizing multi-stage architectures and achieving miniaturization alongside intelligent functionalities will enable more efficient heat dissipation. These improvements are indispensable for catering to the increasing demands of high-power chips. At the system level, the integration of TEC with liquid cooling or heat pipes will enhance overall thermal management efficiently. The incorporation of TE generation provides new opportunities for constructing sustainable and energy-efficient cooling systems. With continued innovation in materials preparation, device design, and system integration, TEC may pave a way for efficient, reliable, and scalable solutions for the next generation of electronic systems.

Thermoelectric materials, capable of directly converting heat to electricity, have a significant potential in sustainable power generation and thermoelectric cooling. Research in this area focuses on optimizing multiple interdependent and competing thermoelectric parameters to maximize the dimensionless figure-of-merit (ZT). Achieving an optimal ZT value requires materials with a large Seebeck coefficient, an excellent electrical conductivity, and a low thermal conductivity. However, these transport properties are interdependent and often in competition, necessitating a balance between the related parameters. A critical aspect of this optimization involves the trade-off between the Seebeck coefficient and electrical conductivity, and both of which are strongly affected by carrier concentration. Lower carrier concentrations generally enhance the Seebeck coefficient, but reduce the conductivity, whereas higher carrier concentrations favor the conductivity at the cost of a lower Seebeck coefficient. This competition also extends to the effective mass, where an increased effective mass can boost the Seebeck coefficient, but often reduce the conductivity due to the decreased carrier mobility. Effective thermoelectric optimization thus requires balancing enhanced effective mass with a high mobility. Furthermore, the coupling between electronic and lattice thermal conductivities significantly impacts the overall performance, positioning a thermal transport as a pivotal element in this optimization. To improve the ZT at low carrier concentrations, achieving electron-phonon decoupling while enhancing carrier mobility are an effective strategy. Based on some simplified thermoelectric models, this work demonstrated that electron-phonon decoupling could improve the thermoelectric performance at near room temperature under the condition of enhanced carrier mobility. In the narrow region of a low carrier concentration where the Seebeck coefficient could change minimally, the effect of the ratio of electronic conductivity to lattice thermal conductivity on the enhancement of ZT was evaluated. Finally, we emphasized the important role of electron-phonon decoupling in enhancing carrier mobility to optimize the thermoelectric performance.

In this work, a simplified theoretical model was proposed to evaluate a relationship between the ZT enhancement and the ratio of electronic conductivity to lattice thermal conductivity (i.e., the degree of electron-phonon decoupling). A simplified phonon-electron decoupling parameter model was designed via assuming that the Seebeck coefficient and carrier concentration could remain constant. In this model, the increase in electronic thermal conductivity was considered to be consistent with the increase in mobility. The lattice thermal conductivity was primarily affected by some complex factors such as crystal structure, defects, and anisotropy, and was therefore treated as a constant term without detailed consideration. In addition, the single-band Kane model was also utilized under approximate conditions, effectively simulating the impact of electron-phonon decoupling on the thermoelectric performance at near room temperature when enhancing the carrier mobility.

Electronic conductivity and lattice thermal conductivity are two important thermal conductivity parameters in semiconductors, and their difference lies in the mechanism and main carrier of heat conduction. The enhancement of carrier mobility can significantly affect the electronic thermal conductivity without changing the lattice thermal conductivity. Therefore, the improvement of mobility can achieve the enhancement of ZT while unchanging the lattice thermal conductivity, and the improvement effect becomes dominant as the carrier mobility increases when using the electron-phonon decoupling parameter model. In addition, for systems with a lower lattice thermal conductivity, the electronic thermal conductivity can be a low level in order to achieve optimal optimization when using optimization strategies to increase carrier mobility. This indicates that the ratio of electronic conductivity to lattice thermal conductivity (i.e., the degree of electron-phonon decoupling) must be concerned when optimizing ZT by increasing carrier mobility in different systems because this ratio directly determines the extent of ZT improvement. Since the ratio of electronic conductivity to lattice thermal conductivity is usually limited in the range of [0. 1, 10] when the ZT value reaches its peak as a function of carrier concentration, this range ensures that the material can achieve the optimal performance. Also, the ratio of electronic conductivity to lattice thermal conductivity increases with increasing temperature. This indicates that optimizing carrier mobility can have a more significant effect on the improvement of near-room temperature thermoelectric performance. Since the carrier concentration is directly proportional to the electronic thermal conductivity, and the lattice thermal conductivity does not depend on the carrier concentration, there is a positive correlation between the carrier concentration and the ratio of electronic conductivity to lattice thermal conductivity. This means that the electronic thermal conductivity increases quickly as the carrier concentration increases, resulting in an increase in the ratio. Therefore, the decrease in carrier concentration can significantly enhance the degree of electron-phonon decoupling as the carrier mobility increases. The thermoelectric performance can be effectively improved via regulating carrier concentration and optimizing carrier mobility, providing an important theoretical basis for the design and optimization of novel thermoelectric materials. In practical situations, the ratio of electronic conductivity to lattice thermal conductivity is usually limited to the interval [0. 1, 10] when the ZT reaches an optimum value as a function of carrier concentration. Therefore, the improvement range of ZT value can also form different upper and lower limits, thereby restricting the improvement of thermoelectric performance. Although the improvement of carrier mobility can effectively improve the thermoelectric performance, there are differences in the electron-phonon coupling strength of different thermoelectric materials, which can make it difficult to improve the ZT to the theoretical optimal level. The single-band Kane model used is combined with some assumptions to simulate the electron-phonon decoupling discipline that is closer to the actual situation. For instance, the peak of ZT moves in the direction of lower carrier concentration, and achieves a larger increase in amplitude, thus forming a potential optimization area due to the increase in carrier mobility and the enhancement of electroacoustic decoupling (i.e., the deformation potential decreases and the B parameter increases).

This study systematically explored the discipline of electron-phonon decoupling at near room temperature when enhancing the carrier mobility based on the simplified electron-phonon decoupling model and single-band Kane model. The results showed that the ratio of electronic conductivity to lattice thermal conductivity could be concerned when optimizing the thermoelectric performance by increasing the carrier mobility, that is, the electron-phonon decoupling strength. The increase in this ratio with increasing temperature further verified the importance of optimizing the carrier mobility for improving the room-temperature thermoelectric performance. Meanwhile, the enhanced ZT of some thermoelectric materials was evaluated by the model, and the increase was far from the theoretical expectation. For the electron-phonon coupling, this synergistically promoted the shift of the ZT peak toward lower carrier concentrations and achieved significant improvements due to the increase in mobility and electron-phonon decoupling (i.e., the reduction of deformation potential and the improvement of B parameter), revealing a potential optimization range for the near room temperature thermoelectric performance. In summary, how to effectively manipulate electron-phonon decoupling while improving mobility to optimize the near room temperature thermoelectric performance could become a challenge in the field of future thermoelectric cooling.