Sort:
Regular Paper Issue
SegNet-OPC: A Mask Optimization Framework in VLSI Design Flow Based on Semantic Segmentation Network
Journal of Computer Science and Technology 2025, 40(2): 500-512
Published: 31 March 2025
Abstract Collect

With the continuous decrease in the critical dimensions of integrated circuits, mask optimization has become the main challenge in VLSI design. In recent years, thriving machine learning has been gradually introduced in the field of optical proximity correction (OPC). Currently, advanced learning-based frameworks have been limited by low mask printability or large computational overhead. To address these limitations, this paper proposes a learning-based framework named SegNet-OPC, which can generate optimized masks from the target layout at shorter training and turnaround time with higher mask printability. The proposed framework consists of a backbone network and loss terms suitable for mask optimization tasks, followed by a fine-tuning network. The framework yields remarkable improvements over conventional methods, delivering significantly faster turnaround time and superior mask printability and manufacturability. With just 1.25 hours of training, the framework achieves comparable mask complexity while surpassing the state-of-the-art methods, achieving a minimum 3% enhancement in mask printability and an impressive 16.7% improvement in mask manufacturability.

Open Access Issue
Anti-Interference Low-Power Double-Edge Triggered Flip-Flop Based on C-Elements
Tsinghua Science and Technology 2022, 27(1): 1-12
Published: 17 August 2021
Abstract PDF (1.3 MB) Collect
Downloads:195

When the input signal has been interfered and glitches occur, the power consumption of Double-Edge Triggered Flip-Flops (DETFFs) will significantly increase. To effectively reduce the power consumption, this paper presents an anti-interference low-power DETFF based on C-elements. The improved C-element is used in this DETFF, which effectively blocks the glitches in the input signal, prevents redundant transitions inside the DETFF, and reduces the charge and discharge frequencies of the transistor. The C-element has also added pull-up and pull-down paths, reducing its latency. Compared with other existing DETFFs, the DETFF proposed in this paper only flips once on the clock edge, which greatly reduces the redundant transitions caused by glitches and effectively reduces power consumption. This paper uses HSPICE to simulate the proposed DETFF and other 10 DETFFs. The findings show that compared with the other 10 types of DETFFs, the proposed DETFF has achieved large performance indexes in the total power consumption, total power consumption with glitches, delays, and power delay product. A detailed analysis of variance indicates that the proposed DETFF features less sensitivity to process, voltage, temperature, and Negative Bias Temperature Instability (NBTI)-induced aging variations.

Total 2