As performance requirements for bus-based embedded System-on-Chips (SoCs) increase, more and more on-chip application-specific hardware accelerators (e.g., filters, FFTs, JPEG encoders, GSMs, and AES encoders) are being integrated into their designs. These accelerators require system-level tradeoffs among performance, area, and scalability. Accelerator parallelization and Point-to-Point (P2P) interconnect insertion are two effective system-level adjustments. The former helps to boost the computing performance at the cost of area, while the latter provides higher bandwidth at the cost of routability. What's more, they interact with each other. This paper proposes a design flow to optimize accelerator parallelization and P2P interconnect insertion simultaneously. To explore the huge optimization space, we develop an effective algorithm, whose goal is to reduce total SoC latency under the constraints of SoC area and total P2P wire length. Experimental results show that the performance difference between our proposed algorithm and the optimal results is only 2.33% on average, while the running time of the algorithm is less than 17 s.

A complementary metal oxide semiconductor (CMOS) transconductor based on a high performance unity-gain buffer driving the degeneration resistor was used to obtain a highly linear voltage-to-current conversion with considerable reduction of the supply voltage. Simulations show that the transconductor using an 0.18-μm standard CMOS process with a 1.2-V supply voltage has less than -80 dB total harmonic distortion (THD) for a 1-MHz 0.4-V_p-p differential input signal. The third-order intermodulation is less than -63 dB for 0.25 V_p-p differential inputs at 1 MHz. The DC power consumption in the transconductor core is 240 μW. This topology is a feasible solution for low voltage and low power applications.