DRAM-based memory suffers from increasing row buffer conflicts, which causes significant performance degradation and power consumption. As memory capacity increases, the overheads of the row buffer conflict are increasingly worse as increasing bitline length, which results in high row activation and precharge latencies. In this work, we propose a practical approach called Row Buffer Cache (RBC) to mitigate row buffer conflict overheads efficiently. At the core of our proposed RBC architecture, the rows with good spatial locality are cached and protected, which are exempted from being interrupted by the accesses for rows with poor locality. Such an RBC architecture significantly reduces the overheads of performance and energy caused by row activation and precharge, and thus improves overall system performance and energy efficiency. We evaluate RBC architecture using SPEC CPU2006 on a DDR4 memory compared to a commodity baseline memory system. Results show that RBC improves the overall performance by up to $\mathrm{2.24}\mathrm{\times }$ ( $\mathrm{16.1}\mathrm{\%}$ on average) and reduces the memory energy by up to $\mathrm{68.2}\mathrm{\%}$ ( $\mathrm{23.6}\mathrm{\%}$ on average) for single-core simulations. For multi-core simulations, RBC increases the overall performance by up to $\mathrm{1.55}\mathrm{\times }$ ( $\mathrm{17}\mathrm{\%}$ on average) and reduces memory energy consumption by up to $\mathrm{35.4}\mathrm{\%}$ ( $\mathrm{21.3}\mathrm{\%}$ on average).