A three-stage pipeline readout circuit with on-chip self-calibration for computing-in-memory

This paper presents a high-precision three-stage pipeline readout circuit for computing-in-memory (CIM) architectures with on-chip self-calibration. The proposed readout circuit addresses the challenges of precision errors in analog computing and enhances computing throughput. A current subtraction error calibration is proposed to effectively compensate for current mirror mismatches, ensuring accurate bypass current by employing negative feedback and capacitor storage. In addition, a resistance variation calibration is proposed to suppress the non-linearity of current-to-voltage conversion circuits with ADC-assisted offset detection. Furthermore, a three-stage pipeline scheme is proposed to enhance computing throughput by parallel processing. Simulated in a 55 nm process, the proposed current subtraction error calibration improves the precision of adjacent column current subtraction by 58.3% compared to the case without calibration. Moreover, the computing throughput of the proposed readout circuit reaches 1908 giga operations per second (GOPS). Under 8-bit weight input and 8-bit output quantization, the proposed readout circuit demonstrates significant improvements in inference accuracy on MNIST, CIFAR-10, and ImageNet datasets by 7.6%, 6.6%, and 8.9%, respectively.