Low power design and ASIC research of RS code

In order to solve the low-power design of reed-solomon (RS) code, it is carried out from different design levels such as system architecture, RTL level and gate level, etc. And it is practiced in application specific integrated circuit (ASIC) design. The back-end IC design is combined to study the chip that can realize the RS coding function. At the system architecture level, the multiplication operation of Galois field in the RS coding algorithm has problems such as large amount of data operation and high-power consumption in hardware implementation. A method based on a multiplier factor matrix is proposed to optimize the RS coding algorithm. The data operation is reduced by converting multiplication operation to subtraction operation, so as to reduce power consumption. At the RTL level and gate level, the logic synthesis and back-end implementation are constrained to implement the low power design, and the overall power consumption can be reduced by about 60%. The problem of high-power consumption of IC chip is solved, which leads to the decline of chip performance, affects the normal operation of the chip and provides a new direction for the integrated circuit process.