Anti-Interference Low-Power Double-Edge Triggered Flip-Flop Based on C-Elements

Zhengfeng Huang; Xiao Yang; Tai Song; Haochen Qi; Yiming Ouyang; Tianming Ni; Qi Xu

doi:10.26599/TST.2020.9010030

Tsinghua Science and Technology 2022, 27(1): 1-12 https://doi.org/10.26599/TST.2020.9010030

Open Access | Issue | Published: 17 August 2021

Anti-Interference Low-Power Double-Edge Triggered Flip-Flop Based on C-Elements

Show Author's Information Hide Author's Information Zhengfeng Huang, Xiao Yang, Tai Song, Haochen Qi, Yiming Ouyang, Tianming Ni, Qi Xu(

)

School of Electronic Science and Applied Physics, Hefei University of Technology, Hefei 230601, China

School of Computer and Information, Hefei University of Technology, Hefei 230601, China

School of Electrical Engineering, Anhui Polytechnic University, Wuhu 241000, China

Keywords:

low-power, Double-Edge Triggered Flip-Flop (DETFF), glitch, C-element

Cite this article:

Huang Z, Yang X, Song T, et al. Anti-Interference Low-Power Double-Edge Triggered Flip-Flop Based on C-Elements. Tsinghua Science and Technology, 2022, 27(1): 1-12. https://doi.org/10.26599/TST.2020.9010030

Download citation

EndNote(RIS)

BibTeX

771

Views

104

Downloads

Citations

Crossref

WoS

Scopus

CSCD

Abstract Full text About this article

Abstract

When the input signal has been interfered and glitches occur, the power consumption of Double-Edge Triggered Flip-Flops (DETFFs) will significantly increase. To effectively reduce the power consumption, this paper presents an anti-interference low-power DETFF based on C-elements. The improved C-element is used in this DETFF, which effectively blocks the glitches in the input signal, prevents redundant transitions inside the DETFF, and reduces the charge and discharge frequencies of the transistor. The C-element has also added pull-up and pull-down paths, reducing its latency. Compared with other existing DETFFs, the DETFF proposed in this paper only flips once on the clock edge, which greatly reduces the redundant transitions caused by glitches and effectively reduces power consumption. This paper uses HSPICE to simulate the proposed DETFF and other 10 DETFFs. The findings show that compared with the other 10 types of DETFFs, the proposed DETFF has achieved large performance indexes in the total power consumption, total power consumption with glitches, delays, and power delay product. A detailed analysis of variance indicates that the proposed DETFF features less sensitivity to process, voltage, temperature, and Negative Bias Temperature Instability (NBTI)-induced aging variations.

Full text

Abstract

Full text

Outline

About this article

Anti-Interference Low-Power Double-Edge Triggered Flip-Flop Based on C-Elements

Show Author's information Hide Author's Information Zhengfeng Huang, Xiao Yang, Tai Song, Haochen Qi, Yiming Ouyang, Tianming Ni, Qi Xu(

)

School of Electronic Science and Applied Physics, Hefei University of Technology, Hefei 230601, China

School of Computer and Information, Hefei University of Technology, Hefei 230601, China

School of Electrical Engineering, Anhui Polytechnic University, Wuhu 241000, China

Abstract

Keywords: low-power, Double-Edge Triggered Flip-Flop (DETFF), glitch, C-element

References(26)

[1]

B. Yang, Z. Yu, and J. Wei, Design of low-power modern radar SoC based on ASIX, Tsinghua Science and Technology, vol. 19, no. 2, pp. 168-173, 2014.

Google Scholar

[2]

S. Hu, W. Ji, and Y. Wang, Feedback cache mechanism for dynamically reconfigurable VLIW processors, Tsinghua Science and Technology, vol. 22, no. 3, pp. 303-316, 2017.

Google Scholar

[3]

P. Zhao, T. Darwish, and M. Bayoumi, High-performance and low power conditional discharge flip-flop, IEEE Transactions on Very Large Scale Integration Systems, vol. 12, no. 5, pp. 477-484, 2004.

Google Scholar

[4]

B. Kong, S. Kim, and Y. Jun, Conditional-capture flip-flop for statistical power reduction, IEEE Journal of Solid-State Circuits, vol. 36, no. 8, pp. 1263-1271, 2001.

Google Scholar

[5]

H. Kawaguchi and T. Sakurai, A reduced clock-swing flip-flop (RCSFF) for 63% power reduction, IEEE Journal of Solid-State Circuits, vol. 33, no. 5, pp. 807-811, 1998.

Google Scholar

[6]

Y. Dai and J. shen, An explicit-pulsed double-edge triggered JK flip-flop, in Proc. of 2009 International Conference on Wireless Communication & Signal Processing, Nanjing, China, 2009, pp. 1-4.

[7]

P. Zhao, J. McNeely, P. Golconda, M. A. Bayoumi, R. A. Barcenas, and W. Kuang, Low-power clock branch sharing double-edge triggered flip-flop, IEEE Transactions on Very Large Scale Integration Systems, vol. 15, no. 3, pp. 338-345, 2007.

Google Scholar

[8]

C. Kim and S.-M. Kang, A low-swing clock double-edge triggered flip-flop, IEEE Journal of Solid-State Circuits, vol. 37, no. 5, pp. 648-652, 2002.

Google Scholar

[9]

S. C. Tiwari, K. Singh, and M. Gupta, A low power high density double edge triggered flip flop for low voltage systems, in Proc. of International Conference on Advances in Recent Technologies in Communication and Computing, Kottayam, India, 2010, pp. 377-380.

[10]

N. Nedovic and V. G. Oklobdzija, Dual-edge triggered storage elements and clocking strategy for low-power systems, IEEE Transaction on VLSI Systems, vol. 13, no. 5, pp. 577-590, 2005.

Google Scholar

[11]

C. C. Yu, Low-power double edge-triggered flip-flop circuit design, in Proc. of 3rd Innovative Computing Information and Control International Conference, Washington, DC, USA, 2008, p. 566.

[12]

S. Kim, J. Kim, and S. Y. Hwang, New path balancing algorithm for glitch power reduction, IEEE Proceedings-Circuits, Devices and Systems, vol. 148, no. 3, pp. 151-156, 2001.

Google Scholar

[13]

M. Pedram, Q. Wu, and X. Wu, A new design of double edge triggered flip-flops, in Proc. of Asian and South Pacific Design Automation Conference, Yokohama, Japan, 1998, pp. 417-421.

[14]

A. Khan, D. Shaikh, and M. T. Beg, 2 GHz low power double edge triggered flip-flop in 65 nm CMOS technology, in Proc. 2012 IEEE International Conference on Signal Processing, Computing and Control, Waknaghat Solan, India, 2012, pp. 1-5.

[15]

S. V. Devarapalli, P. Zarkesh-Ha, and S. C. Suddarth, A robust and low power dual data rate (DDR) flip-flop using C-elements, in Proc. of 11th International Symposium on Quality Electronic Design (ISQED), San Jose, CA, USA, 2010, pp. 147-150.

[16]

N. A. Sabu and K. Batri, Design and analysis of power efficient TG based dual edge triggered flip-flops with stacking technique, Journal of Circuits, Systems and Computers, vol. 29, no. 8, p. 2050123, 2020.

Google Scholar

[17]

Y. Ye, S. Borkar, and V. De, A new technique for standby leakage reduction in high-performance circuits, in Symposium on VLSl Circuits Digest of Technical Papers, Honolulu, HI, USA, 1998, p. 98CH36215.

[18]

D. E. Muller and W. S. Bartky, A theory of asynchro-nous circuits, in Proceedings of International Symposium on the Theory of Switching. Cambridge, MA, USA: Harvard University Press, 1959, pp. 204-243.

[19]

S. Lapshev and S. M. R. Hasan, New low glitch and low power DET flip-flops using multiple C-elements, IEEE Transactions on Circuits & Systems I Regular Papers, vol. 63, no. 10, pp. 1673-1681, 2016.

Google Scholar

[20]

M. Shams, J. C. Ebergen, and M. I. Elmasry, Modeling and comparing CMOS implementations of the C-element, IEEE Transactions on Very Large Scale Integration Systems, vol. 6, no. 4, pp. 563-567, 1998.

Google Scholar

[21]

J. Tschanz, S. Narendra, Z. Chen, S. Borkar, M. Sachdev, and V. De, Comparative delay and energy of single edge-triggered and dual edge-triggered pulsed flip-flops for high-performance microprocessors, in Proc. of International Symposium on Low Power Electronics and Design, Huntington Beach, CA, USA, 2001, pp. 147-152.

[22]

R. Shandilya and R. K. Sharma, High speed low power dual-edge triggered D flip-flop, in Proc. of 2017 International Conference on Intelligent Computing and Control (I2C2), Coimbatore, India, 2017, pp. 1-5.

[23]

I. C. Wey, B. C. Wu, C. C. Peng, C. S. A. Gong, and C. H. Yu, Robust C-element design for soft-error mitigation,IEICE Electronics Express, vol. 12, no. 10, p. 20150268, 2015.

Google Scholar

[24]

Predictive Technology Model (PTM) for SPICE, http://ptm.asu.edu/.

[25]

Yongmin Lee and Yoonmyung Lee, A PVT variation-tolerant static single-phase clocked dual-edge triggered flip-flop for aggressive voltage scaling, IEICE Electronics Express, vol. 16, no. 20, p. 20190528, 2019.

Google Scholar

[26]

Y. Zhang, M. Khayatzade, K. Yang, M. Saligane, N. Pinckney, M. Alioto, D. Blaauw, and D. Sylvester, iRazor: Current-based error detection and correction scheme for PVT variation in 40-nm ARM Cortex-R4 Processor, IEEE Journal of Solid-State Circuits, vol. 53, no. 2, pp. 619-631, 2018.

Google Scholar

About this article

Publication history

Acknowledgements

Rights and permissions

Publication history

Received: 30 July 2020

Accepted: 01 September 2020

Published: 17 August 2021

Issue date: February 2022

Copyright

Acknowledgements

This work was supported in part by the National Natural Science Foundation of China (Nos. 61874156, 61874157, 61904001, and 61904047).

Rights and permissions

The articles published in this open access journal are distributed under the terms of the Creative Commons Attribution 4.0 International License (http://creativecommons.org/licenses/by/4.0/).