Scalable p-type Te_1-xSe_x thin-film transistors and low-power complementary logic gates

Despite the promise of Te as a p-type channel material, realizing Te-based thin-film transistors (TFTs) with low off-state current and high on/off ratio is challenging due to its small bandgap and high background carrier density. Se-alloying offers a potential solution to mitigate these limitations, yet the device performance has remained suboptimal. In this work, through the synergy of stoichiometric control and thickness engineering, we achieve an optimal trade-off between charge transport and switching characteristics in Te_1-xSe_x TFTs. The resulting devices exhibit an average field-effect mobility of 16.8 cm² V^-1 s^-1, I_on/I_off ratio of 1.3×10⁵ and an ultralow off-state current of 10 pA μm^-1. The fabrication process is fully compatible with established low-temperature TFT technologies, enabling high-yield production of transistor arrays with favorable electrical uniformity. Notably, the devices demonstrate exceptional environmental stability, retaining critical performance metrics after six months of storage without encapsulation. Complementary logic gates (NOT, NAND, and NOR) are fabricated by integrating p-Te_0.63Se_0.37 and n-IGZO TFTs. The inverter achieves a high voltage gain of 28, a noise margin of 92.3%, and a low static power consumption of 420 pW at 3 V supply voltage. This study highlights the potential of Te_1-xSe_x as a scalable p-type channel material, advancing the development of TFT-based logic circuits.