High driving current and enhanced gate control in 1-nm gate length type-Ⅱ ZnO/GaN vdWH field-effect transistor via a constituent-layer-selective doping strategy

Two-dimensional (2D) semiconductors provide promising channels for sub-3 nm field-effect transistors (MOSFETs) due to their atomic thickness and strong electrostatic control. At this scale, conventional 2D MOSFETs face a trade-off between driving current and gate control: high source/drain (S/D) doping increases current but weakens gate modulation, whereas low doping improves electrostatics but reduces current. Here, we propose a layer-selective doping (LSD) strategy for the S/D electrodes of type-II ZnO/GaN MOSFETs, which exhibit an intrinsic staggered band alignment that spatially separates electrons and holes. In LSD-ZnO/GaN MOSFETs, only the constituent ZnO layer in the S/D electrodes is n-type doped, while the GaN layer remains intrinsic, spatially separating electrons and holes. Fully doped S/D electrodes of ZnO/GaN MOSFETs (FD-ZnO/GaN MOSFETs), where both ZnO and GaN layers are n-type doped, serve as a reference. Quantum transport simulations show that both FD- and LSD-ZnO/GaN MOSFETs achieve sufficient driving current at sub-3 nm gate lengths. Notably, LSD-ZnO/GaN MOSFETs reach high on-currents of 1493 μA/μm (high-performance) and 392 μA/μm (low-power) with a minimal subthreshold swing of 78 mV/dec at an optimal 1 nm gate length, outperforming previously reported 2D MOSFETs. These improvements of LSD-ZnO/GaN MOSFETs arise from current confinement, which reduces channel capacitance, suppresses leakage current, and mitigates drain-induced barrier lowering, thereby enhancing gate control. The proposed LSD strategy is compatible with the existing layer-by-layer doping technique. It offers a transferable design concept for constituent-layer-selective carrier modulation in other type-II van der Waals heterostructures in sub-3 nm (including 1 nm) logic devices.