Hardware Acceleration Design of HEVC Entropy Encoding Syntax Elements Based on FPGA

High Efficiency Video Coding (HEVC/H. 265) is a widely used video coding standard in the international market. As the core encoding method of HEVC video encoding, Context Adaptive Binary Arithmetic Coding (CABAC) can improve the compression efficiency of arithmetic coding by establishing a more accurate probability model. Moreover, HEVC defines a larger variety of syntax elements and establishes more complex coding structures, further reducing information redundancy and thus reducing the bit rate. However, as the input data to CABAC, syntax elements’high complexity of preprocessing process increases the difficulty of hardware parallel processing. As a result, the throughput rate of entropy coding hardware is difficult to improve, which becomes one of the bottlenecks for HEVC encoder to achieve higher resolution real-time coding. To further speed up the entropy encoding modules, this study designed a high-throughput CABAC entropy encoding architecture based on FPGA. Within the architecture, the pre-header information coding, pre-initialization and coding unit (CU) are able to accelerate the generation of syntax elements, which is dedicated to CABAC. Due to the scheme of efficient residual coding and partial context index pipeline computing, the reduction of path latency and the improvement of operating frequency can be achieved as well as high throughput. In this study, the proposed design, which is synthesized by using a 90 nm standard cell library, occupies a total of 2.099×10⁴ logic gates and operates in the frequency of 200 MHz. This paper also simulated the video sequence provided by HEVC official, and counted the time required for encoding a coding tree unit (CTU) under different quantitative parameters (QP). The experimental statistics show that the time of encoding a CTU was saved by 38.2% on average.