Modeling of 3D NAND Memory Cells with Taper Angle and Programming Strategy Optimization

With the continuous increase in the number of stacking layers in 3D NAND flash memory, the aspect ratio caused by deep hole etching processes also increases accordingly. The resulting taper angle leads to a broadening of the threshold voltage distribution of memory cells, adversely affecting device storage reliability. Current solutions to this problem primarily include process-based methods such as etching optimization and channel compensation, or strategies like error correction coding and read-retry. However, these approaches generally face challenges such as implementation complexity and high hardware overhead. To overcome these limitations and effectively mitigate the impact of the taper angle, a simulation model of a memory string incorporating taper angles is first constructed based on the Sentaurus TCAD platform, validating and analyzing the influence of deep hole taper on the threshold voltage distribution gradient. On this basis, a strategy for dynamic optimization of the pass voltage amplitude in adjacent cells is proposed. This strategy differentially optimizes the pass voltage of word lines adjacent to the target memory cell according to its vertical position in the memory string, thereby accurately compensating for the longitudinal voltage gradient induced by channel taper. Simulation results demonstrate that compared to conventional programming strategy, the proposed strategy optimizes the maximum voltage difference and the standard deviation of distribution, achieving reductions of 62.4% and 61.4%, respectively, in linear mode, and 63.7% and 64.3% in nonlinear mode, while constraining the threshold voltage disturbance of adjacent cells within 3 mV and maintaining stable programming speed.