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Publishing Language: Chinese | Open Access

Progress of two-dimensional semiconductor transistors and integrated circuits

Rongxiang DINGLan WENYukai ZHANGMengjian ZHU ( )
Hunan Provincial Key Laboratory of Novel Nano-optoelectronic Information Materials and Devices, College of Advanced Interdisciplinary Studies, National University of Defense Technology, Changsha 410073, China
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Abstract

Significance

The continuous scaling of transistor feature size has been the core driving force for integrated circuit development over the past half-century. However, as process nodes enter the sub-1 nm regime, silicon-based technology faces fundamental physical bottlenecks, including short-channel effects, mobility degradation, and interconnect delays. 2D (two-dimensional) semiconductors, particularly TMD (transition metal dichalcogenide) such as MoS2, have emerged as promising alternative channel materials due to their atomic-scale thickness, excellent electrostatic control, and immunity to short-channel effects. The IRDS(International roadmap for devices and systems) has listed 2D semiconductors as the leading candidate for future replacement channel materials since 2018, with industry leaders such as IMEC, TSMC, and Intel actively pursuing 2D semiconductor research and development roadmaps. By 2025, MoS2-based CPUs and CMOS circuits have entered preliminary pilot stages, marking the transition of this technology from laboratory research to industrial applications. This review systematically examines the full-chain progress of 2D semiconductors from material synthesis to system integration, covering multiple aspects including materials science, device physics, process integration, and circuit design. By synthesizing recent advances and identifying key challenges, it aims to provide a useful reference for researchers working at the interface of fundamental materials science and practical device engineering.

Progress

This review comprehensively summarizes the research progress of 2D semiconductors across four key dimensions:

Material Synthesis: The review details the evolution of wafer-scale synthesis techniques for 2D semiconductors, with MoS2 as the primary representative. It covers large-area film preparation strategies such as face-to-face precursor transport, modular precursor regulation systems, and 12-inch wafer growth. Regarding crystal domain orientation control, it systematically discusses thermal strategies including step-edge induction and surface symmetry reduction, as well as kinetic strategies involving interface reconstruction layers. The review also presents recent breakthroughs in multilayer film growth, including step-induced uniform nucleation, layer-by-layer epitaxy, and lattice diffusion-interface epitaxy methods that enable the growth of pure-phase rhombohedral (3R) TMD single crystals with up to 15,000 layers. Beyond MoS2, it highlights advances in the synthesis of WS2, WSe2, hBN, Bi2O2Se, and InSe wafers.

Core Process Modules: The review provides an in-depth analysis of contact engineering, gate dielectric integration, and device architecture evolution. For N-type contacts, it covers atomic layer bonding (~70 Ω·μm), edge contacts (~290 Ω·μm), semimetal contacts (Sb: 42 Ω·μm, Bi: 123 Ω·μm), and van der Waals transfer techniques. For P-type contacts, it summarizes bulk doping (Nb: WSe2), chemical doping (PtCl4: 230~320 Ω·μm), van der Waals heterojunction band engineering (41 Ω·μm), and interface intercalation (Se/Au/WSe2: 540 Ω·μm). The review also addresses CGP (contact gate pitch) scaling challenges, highlighting advances in composite metal stacks (CGP=60 nm) and single-crystalline Sb contacts (CGP < 40 nm). For gate dielectrics, it discusses high-κ van der Waals dielectrics, native oxides (Bi2SeO5, κ~22), and single-crystalline metal-oxide dielectrics (c-Al2O3) with interface trap densities as low as 8.4×109 cm-2eV-1. Device architecture innovations, including FinFETs, GAAFETs, MBCFETs, and CFETs based on 2D materials, are also systematically reviewed.

Integrated Circuits: The review traces the development trajectory of 2D semiconductor integrated circuits from early single-transistor demonstrations (2011) to recent RISC-V processors with 5,900 transistors (2025). It highlights key milestones including the first logic gates (2012), 1-bit microprocessors (2017), polarity-controllable transistors (2018), wafer-scale transistor arrays (2020), 1.28 GHz ring oscillators (2023), monolithic 3D integration (2024), and the first full-featured 2D flash chips (2025). The review also discusses emerging applications beyond von Neumann architectures, including in-sensor computing and neuromorphic devices.

Industrialization Pathway: The review analyzes the current challenges in industrialization, including the lack of dedicated equipment, standardized precursors, and design ecosystems. It proposes a three-tiered framework for application scenarios: substitution (ultra-scaled transistors, flexible electronics, ultra-low-power devices), complement (back-end-of-line transistors, in-sensor computing, emerging memories), and beyond (neuromorphic computing, quantum technologies).

Conclusions and Prospects

Two-dimensional semiconductor integrated circuits have evolved from single-device demonstrations to complex system validations and early industrialization exploration over the past decade. Significant breakthroughs have been achieved in single-crystal film preparation, contact resistance engineering, and gate-all-around device architectures, validating the scientific feasibility of 2D semiconductors as critical technological options for the post-Moore era. However, the path toward large-scale industrialization remains challenging, requiring coordinated efforts in material uniformity, device reliability, design ecosystem development, supply chain construction, and cost competitiveness.

The review concludes that 2D semiconductors are unlikely to simply replicate the substitution path of silicon technology but will reshape the semiconductor industry landscape through differentiated complementarity and paradigm innovation. In the near term, they will serve as functional extenders integrated with silicon systems through back-end-of-line integration and in-sensor computing. In the mid-term, with improved material quality and process maturity, they are expected to achieve substitutional breakthroughs in silicon-limited domains such as ultra-scaled transistors and flexible electronics. In the long term, their unique quantum properties may enable beyond-silicon innovations in neuromorphic computing and quantum technologies. Sustained fundamental research investment, open industrial ecosystem collaboration, and application-driven engineering development will be the core drivers for the success of this atomically thin materials revolution.

CLC number: TN386 Document code: A Article ID: 1001-2486(2026)03-162-20

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Journal of National University of Defense Technology
Pages 162-181

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Cite this article:
DING R, WEN L, ZHANG Y, et al. Progress of two-dimensional semiconductor transistors and integrated circuits. Journal of National University of Defense Technology, 2026, 48(3): 162-181. https://doi.org/10.11887/j.issn.1001-2486.26010051

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Received: 22 January 2026
Published: 01 June 2026
© 2026 Journal of National University of Defense Technology

This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/).