AI Chat Paper
Note: Please note that the following content is generated by AMiner AI. SciOpen does not take any responsibility related to this content.
{{lang === 'zh_CN' ? '文章概述' : 'Summary'}}
{{lang === 'en_US' ? '中' : 'Eng'}}
Chat more with AI
Article Link
Collect
Submit Manuscript
Show Outline
Outline
Show full outline
Hide outline
Outline
Show full outline
Hide outline
Research Article

Polarity control of carrier injection for nanowire feedback field-effect transistors

Doohyeok LimSangsig Kim ( )
Department of Electrical Engineering,Korea University, 145 Anam-ro, Seongbuk-gu,Seoul,02841,Republic of Korea;
Show Author Information

Graphical Abstract

Abstract

We present polarity control of the carrier injection for a feedback field-effect transistor (FBFET) with a selectively thinned p+-i-n+ Si nanowire (SiNW) channel and two separate gates. The SiNW FBFET can be reconfigured in the p- or n-channel operation modes via simple control of electric signals. The two separate gates induce potential barriers in the SiNW channel for selective control of the carrier injection. In contrast to previously reported reconfigurable transistors, our transistor features symmetry of the electrical characteristics for the p- and n-channel operation modes. Positive-feedback operation of the SiNW FBFET provides superior switching characteristics for the p- and n-type configurations, including the on/off ratios (~ 105) and subthreshold swings (1.36–1.78 mV/dec). This novel transistor is a promising candidate for reconfigurable electronics.

Electronic Supplementary Material

Download File(s)
12274_2019_2477_MOESM1_ESM.pdf (1.7 MB)

References

1

Brown, S. D.; Francis, R. J.; Rose, J.; Vranesic, Z. G. Field-programmable Gate Arrays; Springer: Boston, MA, USA, 1992.

2

Zhong, Z. H.; Wang, D. L.; Cui, Y.; Bockrath, M. W.; Lieber, C. M. Nanowire crossbar arrays as address decoders for integrated nanosystems. Science 2003, 302, 1377-1379.

3

Strukov, D. B.; Snider, G. S.; Stewart, D. R.; Williams, R. S. The missing memristor found. Nature 2008, 453, 80-83.

4

Xia, Q. F.; Robinett, W.; Cumbie, M. W.; Banerjee, N.; Cardinali, T. J.; Yang, J. J.; Wu, W.; Li, X. M.; Tong, W. M.; Strukov, D. B. et al. Memristor-CMOS hybrid integrated circuits for reconfigurable logic. Nano Lett. 2009, 9, 3640-3645.

5

Yang, J. J.; Strukov, D. B.; Stewart, D. R. Memristive devices for computing. Nat. Nanotechnol. 2013, 8, 13-24.

6

Heinzig, A.; Slesazeck, S.; Kreupl, F.; Mikolajick, T.; Weber, W. M. Reconfigurable silicon nanowire transistors. Nano Lett. 2012, 12, 119-124.

7

Trommer, J.; Heinzig, A.; Mühle, U.; Löffler, M.; Winzer, A.; Jordan, P. M.; Beister, J.; Baldauf, T.; Geidel, M.; Adolphi, B. et al. Enabling energy efficiency and polarity control in germanium nanowire transistors by individually gated nanojunctions. ACS Nano 2017, 11, 1704-1711.

8

Ernst, T. Controlling the polarity of silicon nanowire transistors. Science 2013, 340, 1414-1415.

9

Zhang, J.; de Marchi, M.; Sacchetto, D.; Gaillardon, P. E.; Leblebici, Y.; de Micheli, G. Polarity-controllable silicon nanowire transistors with dual threshold voltages. IEEE Trans. Electron Devices 2014, 61, 3654-3660.

10

Heinzig, A.; Mikolajick, T.; Trommer, J.; Grimm, D.; Weber, W. M. Dually active silicon nanowire transistors and circuits with equal electron and hole transport. Nano Lett. 2013, 13, 4176-4181.

11

Simon, M.; Heinzig, A.; Trommer, J.; Baldauf, T.; Mikolajick, T.; Weber, W. M. Top-down technology for reconfigurable nanowire FETs with symmetric on-currents. IEEE Trans. Nanotechnol. 2017, 16, 812-819.

12

Glassner, S.; Zeiner, C.; Periwal, P.; Baron, T.; Bertagnolli, E.; Lugstein, A. Multimode silicon nanowire transistors. Nano Lett. 2014, 14, 6699-6703.

13

Jhaveri, R.; Nagavarapu, V.; Woo, J. C. S. Asymmetric Schottky tunneling source SOI MOSFET design for mixed-mode applications. IEEE Trans. Electron Devices 2009, 56, 93-99.

14

Kim, M.; Jeon, Y.; Kim, Y.; Kim, S. Impact-ionization and tunneling FET characteristics of dual-functional devices with partially covered intrinsic regions. IEEE Trans. Nanotechnol. 2015, 14, 633-637.

15
Padilla, A.; Yeung, C. W.; Shin, C.; Hu, C. M.; Liu, T. J. K. Feedback FET: A novel transistor exhibiting steep switching behavior at low bias voltages. In Proceedings of 2008 IEEE International Electron Devices Meeting, San Francisco, CA, USA, 2008, pp 1-4.https://doi.org/10.1109/IEDM.2008.4796643
16
Yeung, C. W.; Padilla, A.; Liu, T. J. K.; Hu, C. M. Programming characteristics of the steep turn-on/off feedback FET (FBFET). In Proceedings of 2009 Symposium on VLSI Technology, Honolulu, HI, USA, 2009, pp 176-177.
17

Wan, J.; Cristoloveanu, S.; Le Royer, C.; Zaslavsky, A. A feedback silicon-on-insulator steep switching device with gate-controlled carrier injection. Solid State Electron. 2012, 76, 109-111.

18
Wan, J.; Le Royer, C.; Zaslavsky, A.; Cristoloveanu, S. Z2-FET: A zero-slope switching device with gate-controlled hysteresis. In Proceedings of Technical Program of 2012 VLSI Technology, System and Application, Hsinchu, China, 2012, pp 1-4.https://doi.org/10.1109/VLSI-TSA.2012.6210113
19

Wan, J.; Le Royer, C.; Zaslavsky, A.; Cristoloveanu, S. A systematic study of the sharp-switching Z2-FET device: From mechanism to modeling and compact memory applications. Solid State Electron. 2013, 90, 2-11.

20

Jeon, Y.; Kim, M.; Lim, D.; Kim, S. Steep subthreshold swing n- and p-channel operation of bendable feedback field-effect transistors with p+-i-n+ nanowires by dual-top-gate voltage modulation. Nano Lett. 2015, 15, 4905-4913.

21
Zhang, J.; de Marchi, M.; Gaillardon, P. E.; de Micheli, G. A Schottky-barrier silicon FinFET with 6.0 mV/dec subthreshold slope over 5 decades of current. In Proceedings of 2014 IEEE International Electron Devices Meeting, San Francisco, CA, USA, 2014, pp 13.4.1-13.4.4.https://doi.org/10.1109/IEDM.2014.7047045
22
Lu, Z.; Collaert, N.; Aoulaiche, M.; de Wachter, B.; de Keersgieter, A.; Fossum, J. G.; Altimime, L.; Jurczak, M. Realizing super-steep subthreshold slope with conventional FDSOI CMOS at low-bias voltages. In Proceedings of 2010 International Electron Devices Meeting, San Francisco, CA, USA, 2010, pp 16.6.1-16.6.3.https://doi.org/10.1109/IEDM.2010.5703377
23

Jeon, Y.; Kim, M.; Kim, Y.; Kim, S. Switching characteristics of nanowire feedback field-effect transistors with nanocrystal charge spacers on plastic substrates. ACS Nano 2014, 8, 3781-3787.

24

Lee, B. H.; Ahn, D. C.; Kang, M. H.; Jeon, S. B.; Choi, Y. K. Vertically integrated nanowire-based unified memory. Nano Lett. 2016, 16, 5909-5916.

25

Lim, D.; Kim, M.; Kim, Y.; Kim, S. Memory characteristics of silicon nanowire transistors generated by weak impact ionization. Sci. Rep. 2017, 7, 12436.

Nano Research
Pages 2509-2514
Cite this article:
Lim D, Kim S. Polarity control of carrier injection for nanowire feedback field-effect transistors. Nano Research, 2019, 12(10): 2509-2514. https://doi.org/10.1007/s12274-019-2477-6
Topics:

824

Views

26

Crossref

N/A

Web of Science

25

Scopus

0

CSCD

Altmetrics

Received: 02 April 2019
Revised: 08 June 2019
Accepted: 12 July 2019
Published: 01 August 2019
© Tsinghua University Press and Springer-Verlag GmbH Germany, part of Springer Nature 2019
Return