Journal Home > Volume 11 , Issue 5

In this study, we propose complementary metal-oxide-semiconductor (CMOS) NOR logic gates consisting of silicon nanowire (NW) arrays on bendable substrates. A circuit consisting of two p-channel NW field-effect transistors (NWFETs) in series and two n-channel NWFETs in parallel is constructed to operate a two-input CMOS NOR logic gate. The NOR logic gates operate at a low supply voltage of 1 V with a rail-to-rail logic swing and a high voltage gain of approximately?3.0. The exact NOR logic functionality is achieved owing to the superior electrical characteristics of the well-aligned p- and n-NWFETs, which are obtained using conventional Si-based CMOS technology. Moreover, the NOR logic gates exhibit stable characteristics and have good mechanical properties. The proposed bendable NW CMOS NOR logic gates are promising building blocks for future bendable integrated electronics.


menu
Abstract
Full text
Outline
Electronic supplementary material
About this article

Silicon nanowire CMOS NOR logic gates featuring one-volt operation on bendable substrates

Show Author's information Jeongje Moon1,2Yoonjoong Kim1Doohyeok Lim1Sangsig Kim1( )
Department of Electrical EngineeringKorea University, 145 Anam-ro, Seongbuk-guSeoul02841Republic of Korea
LED PKG Development GroupSamsung Electronics Co. Ltd., 1 Samsung-ro, Yongin-siGyeonggi-do17113Republic of Korea

Abstract

In this study, we propose complementary metal-oxide-semiconductor (CMOS) NOR logic gates consisting of silicon nanowire (NW) arrays on bendable substrates. A circuit consisting of two p-channel NW field-effect transistors (NWFETs) in series and two n-channel NWFETs in parallel is constructed to operate a two-input CMOS NOR logic gate. The NOR logic gates operate at a low supply voltage of 1 V with a rail-to-rail logic swing and a high voltage gain of approximately?3.0. The exact NOR logic functionality is achieved owing to the superior electrical characteristics of the well-aligned p- and n-NWFETs, which are obtained using conventional Si-based CMOS technology. Moreover, the NOR logic gates exhibit stable characteristics and have good mechanical properties. The proposed bendable NW CMOS NOR logic gates are promising building blocks for future bendable integrated electronics.

Keywords: silicon nanowire, field-effect transistor, NOR logic gate, bendable substrate

References(29)

1

Taur, Y. CMOS design near the limit of scaling. IBM J. Res. Dev. 2002, 46, 213-222.

2

Horowitz, M, ; Alon, E.; Patil, D.; Naffziger, S.; Kumar, R.; Bernstein, K. Scaling, power, and the future of CMOS. In Proceedings of 2005 IEEE International Electron Devices Meeting, IEDM 2005, Washington, DC, USA, 2005, pp 7-15.

3

Haensch, W.; Nowak, E. J.; Dennard, R. H.; Solomon, P. M.; Bryant, A.; Dokumaci, O. H.; Kumar, A.; Wang, X.; Johnson, J. B.; Fischetti, M. V. Silicon CMOS devices beyond scaling. IBM J. Res. Dev. 2006, 50, 339-361.

4

Ma, D. D. D.; Lee, C. S.; Au, F. C. K.; Tong, S. Y.; Lee, S. T. Small-diameter silicon nanowire surfaces. Science 2003, 299, 1874-1877.

5

Goldberger, J.; Hochbaum, A. I.; Fan, R.; Yang, P. D. Silicon vertically integrated nanowire field effect transistors. Nano Lett. 2006, 6, 973-977.

6

Yang, B.; Buddharaju, K. D.; Teo, S. H. G.; Singh, N.; Lo, G. Q.; Kwong, D. L. Vertical silicon-nanowire formation and gate-all-around MOSFET. IEEE Electr. Device Lett. 2008, 29, 791-794.

7

Sheriff, B. A.; Wang, D. W.; Heath, J. R.; Kurtin, J. N. Complementary symmetry nanowire logic circuits: Experimental demonstrations and in silico optimizations. ACS Nano 2008, 2, 1789-1798.

8

Goldberger, J.; Sirbuly, D. J.; Law, M.; Yang, P. ZnO nanowire transistors. J. Phys. Chem. B. 2005, 109, 9-14.

9

Fan, Z. Y.; Ho, J. C.; Jacobson, Z. A.; Razavi, H.; Javey, A. Large-scale, heterogeneous integration of nanowire arrays for image sensor circuitry. Proc. Natl. Acad. Sci. USA 2008, 105, 11066-11070.

10

Svensson, J.; Dey, A. W.; Jacobsson, D.; Wernersson, L. -E. Ⅲ-V nanowire complementary metal-oxide semiconductor transistors monolithically integrated on Si. Nano Lett. 2015, 15, 7898-7904.

11

Fan, Z. Y.; Ho, J. C.; Jacobson, Z. A.; Yerushalmi, R.; Alley, R. L.; Razavi, H.; Javey, A. Wafer-scale assembly of highly ordered semiconductor nanowire arrays by contact printing. Nano Lett. 2008, 8, 20-25.

12

Stoesser, A.; von Seggern, F.; Purohit, S.; Nasr, B.; Kruk, R.; Dehm, S.; Wang, D.; Hahn, H.; Dasgupta, S. Facile fabrication of electrolyte-gated single-crystalline cuprous oxide nanowire field-effect transistors. Nanotechnology 2016, 27, 415205.

13

Wang, M. C. P.; Gates, B. D. Directed assembly of nanowires. Mater. Today 2009, 12, 34-43.

14

Baca, A. J.; Ahn, J. H.; Sun, Y. G.; Meitl, M. A.; Menard, E.; Kim, H. -S.; Choi, W. M.; Kim, D. -H.; Huang, Y.; Rogers, J. A. Semiconductor wires and ribbons for high-performance flexible electronics. Angew. Chem., Int. Ed. 2008, 47, 5524-5542.

15

Xu, J. M. Plastic electronics and future trends in microelectronics. Synth. Met. 2000, 115, 1-3.

16

Kim, D. -H.; Rogers, J. A. Stretchable electronics: Materials strategies and devices. Adv. Mater. 2008, 20, 4887-4892.

17

Kim, H. S.; Won, S. M.; Ha, Y. -G.; Ahn, J. H.; Facchetti, A.; Marks, T. J.; Rogers, J. A. Self-assembled nanodielectrics and silicon nanomembranes for low voltage, flexible transistors, and logic gates on plastic substrates. Appl. Phys. Lett. 2009, 95, 183504.

18

Kang, J.; Moon, T.; Jeon, Y.; Kim, H.; Kim, S. Vertically integrated logic circuits constructed using ZnO-nanowire-based field-effect transistors on plastic substrates. J. Nanosci. Nanotechnol. 2013, 13, 3526-3528.

19

Jin, W. F.; Zhang, K.; Gao, Z. W.; Li, Y. P.; Yao, L.; Wang, Y. L.; Dai, L. CdSe nanowire-based flexible devices: Schottky diodes, metal-semiconductor field-effect transistors, and inverters. ACS Appl. Mater. Interfaces 2015, 7, 13131-13136.

20

Lee, M.; Jeon, Y.; Moon, T.; Kim, S. Top-down fabrication of fully CMOS-compatible silicon nanowire arrays and their integration into CMOS inverters on plastic. ACS Nano 2011, 5, 2629-2636.

21

Lee, M.; Jeon, Y.; Kim, M.; Kim, S. Flexible semi-around gate silicon nanowire tunnel transistors with a sub-kT/q switch. J. Appl. Phys. 2015, 117, 224502.

22

Suo, Z.; Ma, E. Y.; Gleskova, H.; Wagner, S. Mechanics of rollable and foldable film-on-foil electronics. Appl. Phys. Lett. 1999, 74, 1177-1179.

23

Ghosh, S.; Roy, K. Parameter variation tolerance and error resiliency: New design paradigm for the nanoscale era. Proc. IEEE 2010, 98, 1718-1751.

24

Na, J. H.; Kitamura, M.; Arakawa, Y. Complementary two-input NAND gates with low-voltage-operating organic transistors on plastic substrates. Appl. Phys Express 2008, 1, 021803.

25

Geier, M. L.; Prabhumirashi, P. L.; McMorrow, J. J.; Xu, W. C.; Seo, J. -W. T.; Everaerts, K.; Kim, C. H.; Marks, T. J.; Hersam, M. C. Subnanowatt carbon nanotube complementary logic enabled by threshold voltage control. Nano Lett. 2013, 13, 4810-4814.

26

Yu, R. M.; Wu, W. Z.; Ding, Y.; Wang, Z. L. GaN nanobelt-based strain-gated piezotronic logic devices and computation. ACS Nano 2013, 7, 6403-6409.

27

Zhao, Y. D.; Li, Q. Q.; Xiao, X. Y.; Li, G. H.; Jin Y. H.; Jiang, K. L.; Wang, J. P.; Fan, S. S. Three-dimensional flexible complementary metal-oxide-semiconductor logic circuits based on two-layer stacks of single-walled carbon nanotube networks. ACS Nano 2016, 10, 2193-2202.

28

Mongillo, M.; Spathis, P.; Katsaros, G.; Gentile, P.; De Franceschi S. Multifunctional devices and logic gates with undoped silicon nanowires. Nano Lett. 2012, 12, 3074-3079.

29

Lee, Y. T.; Raza, S. R. A.; Jeon, P. J.; Ha, R.; Choi, H. -J.; Im, S. Long single ZnO nanowire for logic and memory circuits: NOT, NAND, NOR gate, and SRAM. Nanoscale 2013, 5, 4181-4185.

File
12274_2017_1889_MOESM1_ESM.pdf (882.8 KB)
Publication history
Copyright
Acknowledgements

Publication history

Received: 02 August 2017
Revised: 08 September 2017
Accepted: 16 October 2017
Published: 12 May 2018
Issue date: May 2018

Copyright

© Tsinghua University Press and Springer-Verlag GmbH Germany 2017

Acknowledgements

Acknowledgements

This work was partly supported by the National Research Foundation of Korea (NRF) Grant funded by the Korean Government (MSIP) (Nos. NRF-2013R1A2A1A03070750 and NRF-2015R1A2A1A15055437), the Brain Korea 21 Plus Project in 2017, and Samsung Electronics.

Return