Improved Canny edge detection algorithm based on FPGA

In light of the limited adaptability in threshold selection of the conventional Canny edge detection algorithm and the sluggish processing speed of regular microprocessors, the integration of field-programmable gate array (FPGA) with high-speed parallel processing can significantly enhance the speed of edge detection. This paper presents a refined Canny edge detection algorithm that incorporates an improved dynamic threshold segmentation approach based on local gray value variance to enhance adaptive threshold selection, as well as improve accuracy and robustness in edge detection. The utilization of a bilateral filter effectively reduces noise while preserving image edge gradient information. Furthermore, subregion non-maximum suppression based on gradient direction enhances localization accuracy for image edges. Experimental results validate the feasibility of this adaptive threshold edge detection algorithm, which has shown varying degrees of improvements in single-edge response and edge connectivity compared to traditional Canny algorithms. Moreover, the peak signal-to-noise-ratio (PSNR) of the image processed using this algorithm has been improved by 105% compared to that of the conventional Canny algorithm, and the accuracy and robustness have also been significantly improved.