A balanced computational approach for multilevel VLSI circuit partitioning strategy with bat algorithm

The selection of an appropriate partitioning approach significantly impacts integrated circuit (IC) size and performance. Inaccurate initial partitioning may lead to cascading issues throughout the physical design flow, affecting the performance of subsequent stages in the physical design process. Clustering the chip design into functional units and placing heavily communicating units in proximity can optimize wiring efficiency and improve overall chip performance. In this paper, we introduce a unique application of the bat algorithm (BA) to address the minimum cut cost in partitioning problems. Further, the BA is a nature-inspired metaheuristic algorithm capable of handling intricate and restricted optimization scenarios. The performance of the proposed partitioning with the BA was verified with several experiments on the MCNC and ISPD-98 benchmark datasets.