A Comprehensive Literature Review of AI-Driven Application Mapping and Scheduling Techniques for Network-on-Chip Systems

Network-on-Chip (NoC) systems are progressively deployed in connecting massively parallel megacore systems in the new computing architecture. As a result, application mapping has become an important aspect of performance and scalability, as current trends require the distribution of computation across network nodes/points. In this paper, we survey a large number of mapping and scheduling techniques designed for NoC architectures. This time, we concentrated on 3D systems. We take a systematic literature review approach to analyze existing methods across static, dynamic, hybrid, and machine-learning-based approaches, alongside preliminary AI-based dynamic models in recent works. We classify them into several main aspects covering power-aware mapping, fault tolerance, load-balancing, and adaptive for dynamic workloads. Also, we assess the efficacy of each method against performance parameters, such as latency, throughput, response time, and error rate. Key challenges, including energy efficiency, real-time adaptability, and reinforcement learning integration, are highlighted as well. To the best of our knowledge, this is one of the recent reviews that identifies both traditional and AI-based algorithms for mapping over a modern NoC, and opens research challenges. Finally, we provide directions for future work toward improved adaptability and scalability via lightweight learned models and hierarchical mapping frameworks.