Investigation of Asynchronous Pipeline Circuits Based on Bundled-Data Encoding: Implementation Styles, Behavioral Modeling, and Timing Analysis

As VLSI technology enters the post-Moore era, there has been an increasing interest in asynchronous design because of its potential advantages in power consumption, electromagnetic emission, and automatic speed scaling capacity under supply voltage variations. In most practical asynchronous circuits, a pipeline forms the micro-architecture backbone, and its characteristics play a vital role in determining the overall circuit performance. In this paper, we investigate a series of typical asynchronous pipeline circuits based on bundled-data encoding, spanning different handshake signaling protocols such as 2-phase (micropipeline, Mousetrap, and Click), 4-phase (simple, semi-decoupled, and fully-decoupled), and single-track (GasP). An in-depth review of each selected circuit is conducted regarding the handshaking and data latching mechanisms behind the circuit implementations, as well as the analysis of its performance and timing constraints based on formal behavior models. Overall, this paper aims at providing a survey of asynchronous bundled-data pipeline circuits, and it will be a reference for designers interested in experimenting with asynchronous circuits.