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As VLSI technology enters the post-Moore era, there has been an increasing interest in asynchronous design because of its potential advantages in power consumption, electromagnetic emission, and automatic speed scaling capacity under supply voltage variations. In most practical asynchronous circuits, a pipeline forms the micro-architecture backbone, and its characteristics play a vital role in determining the overall circuit performance. In this paper, we investigate a series of typical asynchronous pipeline circuits based on bundled-data encoding, spanning different handshake signaling protocols such as 2-phase (micropipeline, Mousetrap, and Click), 4-phase (simple, semi-decoupled, and fully-decoupled), and single-track (GasP). An in-depth review of each selected circuit is conducted regarding the handshaking and data latching mechanisms behind the circuit implementations, as well as the analysis of its performance and timing constraints based on formal behavior models. Overall, this paper aims at providing a survey of asynchronous bundled-data pipeline circuits, and it will be a reference for designers interested in experimenting with asynchronous circuits.


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Investigation of Asynchronous Pipeline Circuits Based on Bundled-Data Encoding: Implementation Styles, Behavioral Modeling, and Timing Analysis

Show Author's information Yu Zhou( )
School of Information Science and Technology, Hainan Normal University, Haikou 571158, China

Abstract

As VLSI technology enters the post-Moore era, there has been an increasing interest in asynchronous design because of its potential advantages in power consumption, electromagnetic emission, and automatic speed scaling capacity under supply voltage variations. In most practical asynchronous circuits, a pipeline forms the micro-architecture backbone, and its characteristics play a vital role in determining the overall circuit performance. In this paper, we investigate a series of typical asynchronous pipeline circuits based on bundled-data encoding, spanning different handshake signaling protocols such as 2-phase (micropipeline, Mousetrap, and Click), 4-phase (simple, semi-decoupled, and fully-decoupled), and single-track (GasP). An in-depth review of each selected circuit is conducted regarding the handshaking and data latching mechanisms behind the circuit implementations, as well as the analysis of its performance and timing constraints based on formal behavior models. Overall, this paper aims at providing a survey of asynchronous bundled-data pipeline circuits, and it will be a reference for designers interested in experimenting with asynchronous circuits.

Keywords: asynchronous pipeline circuits, bundled-data encoding, asynchronous circuit modeling

References(67)

[1]
A. Yakovlev, P. Vivet, and M. Renaudin, Advances in asynchronous logic: From principles to GALS & NoC, recent industry applications, and commercial CAD tools, in Proc. 2013 Design, Automation & Test in Europe Conf. & Exhibition (DATE), Grenoble, France, 2013, pp. 1715-1724.
DOI
[2]
S. M. Nowick and M. Singh, Asynchronous design-part 1: Overview and recent advances, IEEE Des. Test, vol. 32, no. 3, pp. 5-18, 2015.
[3]
S. M. Nowick and M. Singh, Asynchronous design-part 2: Systems and methodologies, IEEE Des. Test, vol. 32, no. 3, pp. 19-28, 2015.
[4]
J. Sparsø and S. Furber, Principles of Asynchronous Circuit Design: A Systems Perspective. Dordrecht, The Netherlands: Kluwer Academic Publishers, 2001.
DOI
[5]
P. A. Beerel, R. O. Ozdag, and M. Ferretti, A Designer’s Guide to Asynchronous VLSI. Cambridge, MA, USA: Cambridge University Press, 2010.
DOI
[6]
M. Davies, N. Srinivasa, T. H. Lin, G. Chinya, Y. Q. Cao, S. H. Choday, G. Dimou, P. Joshi, N. Imam, S. Jain, et al., Loihi: A neuromorphic manycore processor with on-chip learning, IEEE Micro, vol. 38, no. 1, pp. 82-99, 2018.
[7]
S. M. Nowick and M. Singh, High-performance asynchronous pipelines: An overview, IEEE Des. Test Comput., vol. 28, no. 5, pp. 8-22, 2011.
[8]
F. Akopyan, J. Sawada, A. Cassidy, R. Alvarez-Icaza, J. Arthur, P. Merolla, N. Imam, Y. Nakamura, P. Datta, G. J. Nam, et al., TrueNorth: Design and tool flow of a 65 mW 1 million neuron programmable neurosynaptic chip, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 34, no. 10, pp. 1537-1557, 2015.
[9]
J. L. Zhang, H. Wu, J. S. Wei, S. J. Wei, and H. Chen, An asynchronous reconfigurable SNN accelerator with event-driven time step update, in Proc. 2019 IEEE Asian Solid-State Circuits Conf. (A-SSCC), Macau, China, 2019, pp. 213-216.
DOI
[10]
M. Roncken, I. Sutherland, C. Chen, Y. Hei, W. Hunt, C. Chau, S. M. Gilla, H. Park, X. Y. Song, A. P. He, et al., How to think about self-timed systems, in Proc. 51st Asilomar Conf. Signals, Systems, and Computers, Pacific Grove, CA, USA, 2017, pp. 1597-1604.
DOI
[11]
J. S. Wei, J. L. Zhang, X. M. Zhang, Z. H. Wu, C. M. Dou, T. Shi, H. Chen, and Q. Liu, An asynchronous AER circuits with rotation priority tree arbiter for neuromorphic hardware with analog neuron, in Proc. 2019 IEEE 13th Int. Conf. ASIC (ASICON), Chongqing, China, 2019, pp. 1-4.
DOI
[12]
Z. Y. Kang, L. Wang, S. S. Guo, R. Gong, Y. Deng, and Q. Dou, ASIE: An asynchronous SNN inference engine for AER events processing, in Proc. 2019 25th IEEE Int. Symp. Asynchronous Circuits and Systems, Hirosaki, Japan, 2019, pp. 48-57.
DOI
[13]
J. L. Zhang, H. Wu, W. J. Chen, S. J. Wei, and H. Chen, Design and tool flow of a reconfigurable asynchronous neural network accelerator, Tsinghua Science and Technology, vol. 26, no. 5, pp. 565-573, 2021.
[14]
W. J. Chen, H. Wu, S. J. Wei, A. P. He, and H. Chen, An asynchronous energy-efficient CNN accelerator with reconfigurable architecture, in Proc. 2018 IEEE Asian Solid-State Circuits Conf. (A-SSCC), Tainan, China, 2018, pp. 51-54.
DOI
[15]
I. E. Sutherland, Micropipelines, Commun. ACM, vol. 32, no. 6, pp. 720-738, 1989.
[16]
M. Singh and S. M. Nowick, MOUSETRAP: High-speed transition-signaling asynchronous pipelines, IEEE Trans. VLSI Syst., vol. 15, no. 6, pp. 684-698, 2007.
[17]
A. Peeters, F. te Beest, M. de Wit, and W. Mallon, Click elements: An implementation style for data-driven compilation, in Proc. 2010 Symp. Asynchronous Circuits and Systems, Grenoble, France, 2010, pp. 3-14.
DOI
[18]
R. L. Traylor, Self-timed data pipeline apparatus using asynchronous stages having toggle flip-flops, U.S. Patent 5386585, January 31, 1995.
[19]
A. Mardari, Z. Jelčicová, and J. Sparsø, Design and FPGA-implementation of asynchronous circuits using two-phase handshaking, in Proc. 2019 25th Int. Symp. Asynchronous Circuits and Systems, Hirosaki, Japan, 2019, pp. 9-18.
DOI
[20]
P. Day and J. V. Woods, Investigation into micropipeline latch design styles, IEEE Trans. VLSI Syst., vol. 3, no. 2, pp. 264-272, 1995.
[21]
S. B. Furber and P. Day, Four-phase micropipeline latch control circuits, IEEE Trans. VLSI Syst., vol. 4, no. 2, pp. 247-253, 1996.
[22]
S. B. Furber and J. Liu, Dynamic logic in four-phase micropipelines, in Proc. 2nd Int. Symp. Advanced Research in Asynchronous Circuits and Systems, Fukushima, Japan, 1996, pp. 11-16.
[23]
J. Cortadella, A. Kondratyev, L. Lavagno, and C. P. Sotiriou, Desynchronization: Synthesis of asynchronous circuits from synchronous specifications, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 25, no. 10, pp. 1904-1921, 2006.
[24]
G. Birtwistle and K. S. Stevens, The family of 4-phase latch protocols, in Proc. 14th IEEE Int. Symp. Asynchronous Circuits and Systems, Newcastle Upon Tyne, UK, 2008, pp. 71-82.
DOI
[25]
K. Y. Yun, P. A. Beerel, and J. Arceo, High-performance asynchronous pipeline circuits, in Proc. 2nd Int. Symp. Advanced Research in Asynchronous Circuits and Systems, Fukushima, Japan, 1996, pp. 17-28.
[26]
R. Kol and R. Ginosar, A doubly-latched asynchronous pipeline, in Proc. Int. Conf. Computer Design VLSI in Computers and Processors, Austin, TX, USA, 1997, pp. 706-711.
[27]
T. H. Y. Meng, R. W. Brodersen, and D. G. Messerschmitt, Automatic synthesis of asynchronous circuits from high-level specifications, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 8, no. 11, pp. 1185-1205, 1989.
[28]
I. Sutherland and S. Fairbanks, GasP: A minimal FIFO control, in Proc. 7th Int. Symp. Asynchronous Circuits and Systems, Salt Lake City, UT, USA, 2001, pp. 46-53.
[29]
K. van Berkel and A. Bink, Single-track handshake signaling with application to micropipelines and handshake circuits, in Proc. 2nd Int. Symp. Advanced Research in Asynchronous Circuits and Systems, Fukushima, Japan, 1996, pp. 122-133.
[30]
M. Ferretti and P. A. Beerel, High performance asynchronous design using single-track full-buffer standard cells, IEEE J. Solid-St. Circ., vol. 41, no. 6, pp. 1444-1454, 2006.
[31]
M. Ferretti and P. A. Beerel, Single-track asynchronous pipeline templates using 1-of-N encoding, in Proc. Conf. DATE, Munich, Germany, 2002, pp. 1008-1015.
[32]
T. E. Williams, Self-timed rings and their application to division, PhD dissertation, Stanford University, Stanford, CA, USA, 1991.
[33]
A. M. Lines, Pipelined asynchronous circuits, Master thesis, California Institute of Technology, Pasadena, CA, USA, 1998.
[34]
M. Singh and S. M. Nowick, The design of high-performance dynamic asynchronous pipelines: Lookahead style, IEEE Trans. VLSI Syst., vol. 15, no. 11, pp. 1256-1269, 2007.
[35]
M. Singh and S. M. Nowick, The design of high- performance dynamic asynchronous pipelines: High-capacity style, IEEE Trans. VLSI Syst., vol. 15, no. 11, pp. 1270-1283, 2007.
[36]
K. Fant, Logically Determined Design: Clockless System Design with NULL Convention Logic. New Jersey, USA: John Wiley & Sons, 2005.
DOI
[37]
H. van Gageldonk, K. van Berkel, A. Peeters, D. Baumann, D. Gloor, and G. Stegmann, An asynchronous low-power 80C51 microcontroller, in Proc. 4th Int. Symp. Advanced Research in Asynchronous Circuits and Systems, San Diego, CA, USA, 1998, pp. 96-107.
[38]
M. Davies, A. Lines, J. Dama, A. Gravel, R. Southworth, G. Dimou, and P. Beerel, A 72-port 10G Ethernet switch/router using quasi-delay-insensitive asynchronous design, in Proc. 20th IEEE Int. Symp. Asynchronous Circuits and Systems, Potsdam, Germany, 2014, pp. 103-104.
DOI
[39]
J. Tse and A. Lines, NanoMesh: An asynchronous kilo-core system-on-chip, in Proc. 19th Int. Symp. Asynchronous Circuits and Systems, Santa Monica, CA, USA, 2013, pp. 40-49.
DOI
[40]
J. Teifel and R. Manohar, Highly pipelined asynchronous FPGAs, in Proc. 2004 ACM/SIGDA 12th Int. Symp. Field Programmable Gate Arrays, Monterey, CA, USA, 2004, pp. 133-142.
DOI
[41]
D. Edwards, W. Toms, S. Temple, L. Plana, J. Garside, and S. Furber, The story of the amulet: A brief history of asynchronous events in Manchester, in This Asynchronous World, Essays dedicated to Alex Yakovlev on the occasion of his 60th birthday. 2nd ed. Newcastle University, Newcastle, UK, 2017, pp. 120-130.
[42]
J. D. Garside, S. B. Furber, S. Temple, and J. V. Woods, The Amulet chips: Architectural development for asynchronous microprocessors, in Proc. 16th Int. Conf. Electronics, Circuits and Systems, Yasmine Hammamet, Tunisia, 2009, pp. 343-346.
DOI
[43]
S. B. Furber, P. Day, J. D. Garside, N. C. Paver, and J. V. Woods, AMULET1: a micropipelined ARM, in Proc. COMPCON ’94, San Francisco, CA, USA, 1994, pp. 476-485.
[44]
S. B. Furber, J. D. Garside, P. Riocreux, S. Temple, P. Day, J. W. Liu, and N. C. Paver, AMULET2e: An asynchronous embedded controller, Proc. IEEE, vol. 87, no. 2, pp. 243-256, 1999.
[45]
J. D. Garside, S. B. Furber, and S. H. Chung, AMULET3 revealed, in Proc. 5th Int. Symp. Advanced Research in Asynchronous Circuits and Systems, Barcelona, Spain, 1999, pp. 51-59.
[46]
D. E. Muller and W. S. Bartky, A theory of asynchronous circuits, in Proceedings of International Symposium on the Theory of Switching, Cambridge, MA, USA, 1957, pp. 204-243.
[47]
H. Wu, Z. Su, J. L. Zhang, S. J. Wei, Z. H. Wang, and H. Chen, A design flow for click-based asynchronous circuits design with conventional EDA tools, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., .
[48]
A. P. He, G. B. Feng, J. L. Zhang, P. F. Li, Y. Hei, and H. Chen, Click-based asynchronous mesh network with bounded bundled data, in Proc. 47th Int. Conf. Parallel Processing, Eugene, OR, USA, 2018, p. 43.
DOI
[49]
L. Y. Rosenblum and A. Yakovlev, Signal graphs: From self-timed to timed ones, in Proc. of International Workshop on Timed Petri Nets, Torino, Italy, 1985, pp. 199-206.
[50]
T. A. Chu, On the models for designing VLSI asynchronous digital systems, Integration, vol. 4, no. 2, pp. 99-113, 1986.
[51]
I. Poliakov, D. Sokolov, and A. Mokhov, Workcraft: A static data flow structure editing, visualisation and analysis tool, in Proc. 28th Int. Conf. Applications and Theory of Petri Nets and other Models of Concurrency, Siedlce, Poland, 2007, pp. 505-514.
DOI
[52]
D. J. Kinniment, Synchronization and Arbitration in Digital Systems. Hoboken, NJ, USA: John Wiley & Sons, 2007.
DOI
[53]
T. Verhoeff, Delay-insensitive codes: An overview, Dist. Comput., vol. 3, no. 1, pp. 1-8, 1988.
[54]
W. J. Bainbridge, W. B. Toms, D. A. Edwards, and S. B. Furber, , point-to-point interconnect using m-of-n codes, in Proc. 9th Int. Symp. Asynchronous Circuits and Systems, Vancouver, Canada, 2003, pp. 132-140.
[55]
V. Varshavsky, V. Marakhovsky, and T. A. Chu, Logical timing (Global synchronization of asynchronous arrays), in Proc. 1st Aizu Int. Symp. Parallel Algorithms/Architecture Synthesis, Fukushima, Japan, 1995, pp. 130-138.
[56]
C. L. Seitz, System timing, in Introduction to VLSI Systems, C. Mead, L. Conway, eds. Reading, MA, USA: Addison-Wesley Publishing, 1980, pp. 218-262.
[57]
C. D. Nielsen, Evaluation of function blocks for asynchronous design, in Proc. Conf. European Design Automation, Grenoble, France, 1994, pp. 454-459.
[58]
J. Sparsø and J. Staunstrup, Delay-insensitive multi-ring structures, Integration, vol. 15, no. 3, pp. 313-340, 1993.
[59]
C. Jeong and S. M. Nowick, Optimization of robust asynchronous circuits by local input completeness relaxation, in Proc. 2007 Asia and South Pacific Design Automation Conf., Yokohama, Japan, 2007, pp. 622-627.
DOI
[60]
Y. Zhou, D. Sokolov, and A. Yakovlev, Cost-aware synthesis of asynchronous circuits based on partial acknowledgement, in Proc. 2006 IEEE/ACM Int. Conf. Computer-Aided Design, San Jose, CA, USA, 2006, pp. 158-163.
DOI
[61]
J. Cortadella, M. Kishinevsky, A. Kondratyev, L. Lavagno, and A. Yakovlev, Logic Synthesis for Asynchronous Controllers and Interfaces. Berlin, Germany: Springer, 2002.
DOI
[62]
J. Cortadella, M. Kishinevsky, A. Kondratyev, L. Lavagno, and A. Yakovlev, Petrify: A tool for manipulating concurrent specifications and synthesis of asynchronous controllers, IEICE Transactions Information and Systems, vol. 80, no. E80-D, pp. 315-325.
[63]
K. Y. Yun and D. L. Dill, Automatic synthesis of extended burst-mode circuits: Part I (specification and hazard-free implementation), IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 18, no. 2, pp. 101-117, 1999.
[64]
K. van Berkel, Beware the isochronic fork, Integration, vol. 13, no. 2, pp. 103-128, 1992.
[65]
J. L. Peterson, Petri Net Theory and the Modeling of Systems. Upper Saddle River, NJ, USA: Prentice-Hall, 1981.
[66]
A. V. Yakovlev, A. M. Koelmans, A. Semenov, and D. J. Kinniment, Modelling, analysis and synthesis of asynchronous control circuits using Petri nets, Integration, vol. 21, no. 3, pp. 143-170, 1996.
[67]
V. I. Varshavsky, Self-timed Control of Concurrent Processes. Dordrecht, the Netherlands: Springer, 1990.
DOI
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Received: 19 March 2021
Revised: 30 June 2021
Accepted: 07 July 2021
Published: 13 November 2021
Issue date: June 2022

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© The author(s) 2022

Acknowledgements

This work was supported in part by the Hainan Academician Innovation Platform (No. YSPTZX202036) and in part by the Hainan Natural Science Foundation (No. 619MS054). The author is grateful to Prof. Alex Yakovlev for his teaching of the STG modeling.

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