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Hardening reliability-critical gates in a circuit is an important step to improve the circuit reliability at a low cost. However, accurately locating the reliability-critical gates is a key prerequisite for the efficient implementation of the hardening operation. In this paper, a probabilistic-based calculation method developed for locating the reliability-critical gates in a circuit is described. The proposed method is based on the generation of input vectors and the sampling of reliability-critical gates using uniform non-Bernoulli sequences, and the criticality of the gate reliability is measured by combining the structure information of the circuit itself. Both the accuracy and the efficiency of the proposed method have been illustrated by various simulations on benchmark circuits. The results show that the proposed method has an efficient performance in locating accuracy and algorithm runtime.


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Uniform Non-Bernoulli Sequences Oriented Locating Method for Reliability-Critical Gates

Show Author's information Jie XiaoZhanhui ShiWeidong ZhuJianhui Jiang( )Qianwei ZhouJungang LouYujiao HuangQiou JiZiwen Sun
Department of Computer Science and Technology, Zhejiang University of Technology, Hangzhou 310023, China.
Department of Software Engineering, Tongji University, Shanghai 201804, China.
Department of Information Science, Huzhou University, Huzhou 313000, China.

Abstract

Hardening reliability-critical gates in a circuit is an important step to improve the circuit reliability at a low cost. However, accurately locating the reliability-critical gates is a key prerequisite for the efficient implementation of the hardening operation. In this paper, a probabilistic-based calculation method developed for locating the reliability-critical gates in a circuit is described. The proposed method is based on the generation of input vectors and the sampling of reliability-critical gates using uniform non-Bernoulli sequences, and the criticality of the gate reliability is measured by combining the structure information of the circuit itself. Both the accuracy and the efficiency of the proposed method have been illustrated by various simulations on benchmark circuits. The results show that the proposed method has an efficient performance in locating accuracy and algorithm runtime.

Keywords: gate-level circuit reliability, uniform non-Bernoulli sequences, reliability-critical gates

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Publication history

Received: 01 April 2019
Revised: 22 August 2019
Accepted: 28 August 2019
Published: 19 June 2020
Issue date: February 2021

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© The author(s) 2021.

Acknowledgements

This work was supported by the National Natural Science Foundation of China (Nos. 61972354, 61432017, 61772199, 61802347, and 61503338), the Natural Science Foundation of Zhejiang Province (Nos. LY18F020028 and LY18F030023), and the Innovative Experiment Project of Zhejiang University of Technology (No. PX-68182112).

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