Ionizing-irradiation-involved integration of ultra-low power CNT-Si 3D CMOS ICs

Three-dimensional complementary metal-oxide-semiconductor technology integrating carbon nanotubes and silicon presents a promising pathway for the fabrication of beyond-Moore integrated circuits. Herein, we present an ionizing-irradiation-involved integration process towards ultra-low-power fabrication, completely compatible with the 3D integration process. As the fundamental building blocks of digital circuits, inverter cells are examined to verify the effectiveness of this proposed methodology. Furthermore, comparative experiments combined with numerical simulations are utilized to thoroughly investigate transistor-level radiation effects, revealing the governing mechanisms of power reduction. By incorporating Cobalt-60 γ-ray irradiation within the wafer-scale 180-nm-node 3D integration, the threshold voltage mismatch between p-type and n-type transistors can be resolved without significant modifications to the process flow. With optimized ionizing radiation doses and bias conditions, the switching threshold voltages of the 3D CMOS inverters improves from 0.400× to 0.495× of the supply voltage V_DD (a 24.2% improvement), closely approaching the ideal value of 0.5× V_DD. This optimization leads to a distinct increase in the noise margin low from 0.276× to 0.373× V_DD (a 35.1% enhancement), significantly boosting the reliability of the digital circuit cells. More importantly, the minimal operational V_DD of the inverters is remarkably reduced from 0.5 to 0.2 V. An ultra-low minimal peak dynamic power of 8.33 pW (831× reduction by the ionizing irradiation) is achieved, which is amongst the lowest values in publications.