Machine learning-guided process co-optimization of flexible carbon nanotube thin-film transistors for low-voltage digital logic circuits

Carbon nanotube thin-film transistors (CNT-TFTs) are promising for flexible electronics, but circuit-oriented optimization remains challenging because reliable logic operation requires a coordinated balance among multiple device metrics, and such a balance is difficult to achieve by one-factor-at-a-time tuning within a coupled multistep fabrication process. Accordingly, process optimization must be target-oriented rather than driven by any single device metric. Here, we develop a machine learning-guided process co-optimization framework for flexible CNT-TFTs and use low-voltage digital logic as a representative use case. A decision-tree model trained on more than 800 devices from 80 fabrication recipes employs a weighted evaluation score that jointly considers extracted field-effect mobility as a proxy for current-drive capability, threshold voltage, drain current at V_GS = 0 V, subthreshold swing, and on/off ratio. The optimized enhancement-mode CNT-TFTs exhibit extracted field-effect mobilities up to 71 cm²·V⁻¹·s⁻¹, a width-normalized drain current at V_GS = 0 V as low as 0.2 pA·μm⁻¹, and an on/off ratio of 10⁶. Using inverters as a sensitive unit-level benchmark, we realize 2 V pseudo-PMOS (PMOS = P-channel metal-oxide-semiconductor) inverters with a switching threshold near V_DD/2, a voltage gain of 60, and noise margins of 36%–42%. The same platform further supports a 5-stage ring oscillator operating at 60 kHz, as well as rail-to-rail basic logic gates and a 1-bit full adder, thereby verifying low-voltage dynamic and cascaded logic operation on flexible CNT-TFTs. These results show that machine learning-guided process co-optimization provides an efficient route for translating circuit requirements into fabrication strategies for flexible CNT logic circuits.