Atomic-layer-selective source/drain doping unlocks high current and strong gate control in 1-nm asymmetric monolayer Ga₂O₃ transistors

As transistor scaling approaches the sub-3 nm regime, particularly the 1 nm technology node, two-dimensional (2D) monolayer metal-oxide-semiconductor field-effect transistors (MOSFETs) face a fundamental limitation arising from the intrinsic coupling between carrier injection and gate electrostatic control. Increasing source/drain (S/D) doping improves carrier injection but degrades electrostatics, whereas reduced doping enhances gate control at the expense of driving current. Here, we propose an atomic-layer-selective doping strategy for S/D electrodes in asymmetric monolayer Ga₂O₃ MOSFETs, exploiting the intrinsic layer-resolved electronic structure of monolayer Ga₂O₃, where electrons are predominantly confined to the bottom Ga–O sublayers while holes reside in the top O–Ga–O sublayers. By n-type locally doping (LD) the bottom Ga–O sublayers while keeping the top O–Ga–O sublayers intrinsic, the LD strategy decouples carrier injection from gate control at the atomic-layer scale. Fully doped S/D electrodes are used as a reference benchmark. Quantum transport simulations show that both fully doped and LD devices deliver high driving currents at gate lengths of 3 and 2 nm. Notably, layer-confined transport in LD devices substantially enhances electrostatic control, with reduced subthreshold swing and suppressed leakage current, enabling simultaneous high current and robust gate electrostatics at 1 nm. Benefiting from its experimental feasibility, the LD technique establishes a materials-guided, transferable design principle for overcoming the current-electrostatics trade-off in sub-3 nm logic devices, applicable to a broad class of 2D asymmetric monolayer semiconductors with spatially separated charge carriers.