Dielectric engineering for scaling down two-dimensional field-effect transistors

For decades, silicon-based technologies, driven by Moore’s Law, have been the cornerstone of information technology. However, the relentless scaling of transistors has brought them close to their physical limits, posing formidable challenges. Two-dimensional field-effect transistors (2D FETs), with their atomic-scale thickness and exceptional electronic properties, have emerged as a promising candidate to sustain Moore’s Law. Achieving high-performance scaling of 2D FETs requires the synergistic optimization of the channel, contacts, and critical gate dielectric layers. Among these, dielectric scaling is particularly crucial and distinctive: on one hand, the atomically thin 2D channels are highly sensitive to gate control, necessitating ultrathin, high-quality dielectric layers to achieve strong gate modulation and reduced power consumption; on the other hand, traditional deposition methods struggle with the chemically inert interfaces of 2D materials, often introducing defects, making the simultaneous reduction of thickness and preservation of near-perfect interface integrity a central challenge. Recently, advancements in novel dielectric fabrication techniques and high-κ materials have enabled the reduction of equivalent oxide thickness (EOT) to 0.28 nm, thereby significantly enhancing device performance. However, achieving sub-0.5-nm EOT while ensuring robust complementary-metal-oxide-semiconductor (CMOS) compatibility remains an open challenge that demands further material and process innovations. Herein, we survey and dissect advances in dielectric scaling for 2D FETs, addressing interfacial integrity preservation through van der Waals (vdW) dielectrics, transfer optimization, in-situ oxidation, and seed-layer engineering. By identifying key bottlenecks and establishing actionable guidelines, this review aims to advance dielectric scaling in 2D FETs and related technologies.