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Research Article | Open Access

A ferroelectric semiconductor floating-gate transistor based on van der Waals heterostructures

Xuanye Liu1,2Hui Gao1,2Peng Song1,2Chijun Wei2Nuertai Jiazila1,2Jiequn Sun1,2Chengze Du1,2Hui Guo1,2,3Yanfeng Guo4Haitao Yang1,2,3 ( )Lihong Bao1,2,3 ( )Sokrates T. Pantelides2,5Hong-Jun Gao1,2,3
Beijing National Center for Condensed Matter Physics and Institute of Physics, Chinese Academy of Sciences, Beijing 100190, China
School of Physical Sciences, University of Chinese Academy of Sciences, Beijing 100049, China
Hefei National Laboratory, Hefei 230088, China
School of Physical Science and Technology, Shanghai Tech University, Shanghai 201210, China
Department of Physics and Astronomy & Department of Electrical and Computer Engineering, Vanderbilt University, Nashville, TN 37325, USA
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Graphical Abstract

A ferroelectric semiconductor floating-gate transistor, where the ferroelectric semiconductor channel α-In2Se3, with interlocked out-of-plane and in-plane polarization, placed on a hexagonal boron nitride/multi-layered graphene/SiO2 floating-gate structure, is demonstrated.

Abstract

With the explosive expansion of information, there is a growing need for non-volatile memories with high storage density and reconfigurability. Emerging two-dimensional (2D) ferroelectric materials enable the design of various high-performance functional devices that can potentially address these challenges. Here, we report a ferroelectric semiconductor floating-gate transistor based on an α-In2Se3/hexagonal boron nitride (h-BN)/multi-layered graphene (MLG) van der Waals heterostructure on a SiO2/Si substrate. Thanks to the coexistence of both out-of-plane and in-plane polarizations in an α-In2Se3 channel, pairs of polarization-modulated channel resistance states can be successfully generated between the floating-gate-modulated on and off states, which can be programmed by either vertical gate pulses or planar drain pulses. These features enable a 2-bit multi-level memory in both three-terminal or two-terminal operational modes, significantly increasing the storage density and reconfigurability. The present results introduce a new design degree of freedom for floating-gate memories and provide fresh insights into future non-volatile memory technologies.

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Nano Research
Article number: 94907425
Cite this article:
Liu X, Gao H, Song P, et al. A ferroelectric semiconductor floating-gate transistor based on van der Waals heterostructures. Nano Research, 2025, 18(6): 94907425. https://doi.org/10.26599/NR.2025.94907425
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Received: 12 February 2025
Revised: 31 March 2025
Accepted: 31 March 2025
Published: 16 May 2025
© The Author(s) 2025. Published by Tsinghua University Press.

This is an open access article under the terms of the Creative Commons Attribution 4.0 International License (CC BY 4.0, https://creativecommons.org/licenses/by/4.0/).

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