Pushing the high-k scalability limit with a superparaelectric gate layer

To meet the expectation set by Moore’s law on transistors, the search for thickness-scalable high dielectric constant (k) gate layers has become an emergent research frontier. Previous investigations have failed to solve the “polarizability-scalability-insulation robust-ness” trilemma. In this work, we show that this trilemma can be solved by using a gate layer of a high k ferroelectric oxide in its superparaelectric (SPE) state. In the SPE, its polar order becomes local and is dispersed in an amorphous matrix with a crystalline size down to a few nanometers, leading to an excellent dimensional scalability and a good field-stability of the k value. As an example, a stable high k value (37±3) is shown in ultrathin SPE films of (Ba_0.95,Sr_0.05)(Zr_0.2,Ti_0.8)O₃ deposited on LaNiO₃-buffered Pt/Ti/SiO₂/(100)Si down to a 4 nm thickness, leading to a small equivalent oxide thickness of ~0.46 nm. The aforementioned characteristic microstructure endows the SPE film a high breakdown strength (~10.5 MV cm^-1 for the 4 nm film), and hence ensures a low leakage current for the operation of the CMOS gate. Lastly, a high electrical fatigue resistance is displayed by the SPE films. These results reveal a great potential of superparaelectric materials as gate dielectrics in the next-generation microelectronics.