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Research Article | Open Access

Pushing the high-k scalability limit with a superparaelectric gate layer

Kun Wang1,2,3Chao Liu1,Yuan Zhang4,Fuyu Lv1,Jun Ouyang1,2,5( )Houbing Huang6( )Rui-Long Yang7Yu-Yao Zhao2Hongbo Cheng1Hanfei Zhu1Xiaoming Shi6Yun Tian2
Institute of Advanced Energy Materials and Chemistry, Jinan Engineering Laboratory for Multi-scale Functional Materials, School of Chemistry and Chemical Engineering, Qilu University of Technology (Shandong Academy of Sciences), Jinan 250353, China
Key Laboratory for Liquid-Solid Structure Evolution and Processing of Materials (Ministry of Education), School of Materials Science and Engineering, Shandong University, Jinan 250061, China
China Tobacco Shandong Industrial Co., Ltd., Jinan 250104, China
Department of Materials Science and Engineering, Southern University of Science and Technology, Shenzhen 518055, China
Key Laboratory of Key Film Materials & Application for Equipments (Hunan Province), School of Material Sciences and Engineering, Xiangtan University, Xiangtan 411105, China
Advanced Research Institute of Multidisciplinary Science, and School of Materials Science and Engineering, Beijing Institute of Technology, Beijing 100081, China
Key Laboratory of Magnetic Molecules and Magnetic Information Materials of Ministry of Education, School of Chemistry and Materials Science, Shanxi Normal University, Taiyuan 030032, China

Chao Liu, Yuan Zhang, and Fuyu Lv contributed equally to this work.

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Graphical Abstract


To meet the expectation set by Moore’s law on transistors, the search for thickness-scalable high dielectric constant (k) gate layers has become an emergent research frontier. Previous investigations have failed to solve the “polarizability–scalability–insulation robustness” trilemma. In this work, we show that this trilemma can be solved by using a gate layer of a high k ferroelectric oxide in its superparaelectric (SPE) state. In the SPE, its polar order becomes local and is dispersed in an amorphous matrix with a crystalline size down to a few nanometers, leading to an excellent dimensional scalability and a good field-stability of the k value. As an example, a stable high k value (37±3) is shown in ultrathin SPE films of (Ba0.95,Sr0.05)(Zr0.2,Ti0.8)O3 deposited on LaNiO3-buffered Pt/Ti/SiO2/(100)Si down to a 4 nm thickness, leading to a small equivalent oxide thickness of ~0.46 nm. The aforementioned characteristic microstructure endows the SPE film a high breakdown strength (~10.5 MV·cm−1 for the 4 nm film), and hence ensures a low leakage current for the operation of the complementary metal oxide semiconductor (CMOS) gate. Lastly, a high electrical fatigue resistance is displayed by the SPE films. These results reveal a great potential of superparaelectric materials as gate dielectrics in the next-generation microelectronics.

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Journal of Advanced Ceramics
Pages 539-547
Cite this article:
Wang K, Liu C, Zhang Y, et al. Pushing the high-k scalability limit with a superparaelectric gate layer. Journal of Advanced Ceramics, 2024, 13(4): 539-547.








Web of Science






Received: 01 March 2024
Revised: 02 March 2024
Accepted: 06 March 2024
Published: 30 April 2024
© The Author(s) 2024.

This is an open access article under the terms of the Creative Commons Attribution 4.0 International License (CC BY 4.0,