Area optimization approach for MPRM logic circuits based on multi-strategy synergy ant lion optimization algorithm

In this paper, we propose a multi-strategy synergy ant lion optimization (MSALO) algorithm to address the problems of insufficient optimization efficacy of existing mixed polarity Reed-Muller (MPRM) circuit area optimization methods. A two-strategy random tour mechanism is used in the algorithm’s random tour stage to address the issue of the ant lion optimization (ALO) algorithm’s poor global search ability. A breakout mechanism is used for elite ant lion individuals to address the issue of poor local exploration ability. To expedite the convergence rate of the algorithm, an adaptive ant position update strategy based on the sine function is introduced. The MPRM circuit area optimization approach based on MSALO is proposed to search for the best polarity corresponding to the MPRM logic circuit with the smallest circuit area by using MSALO. The experimental results based on the Microelectronics Center of North Carolina (MCNC) benchmark test circuit demonstrate that the average area savings rate of the area optimization strategy based on MSALO may be increased by an average of 27.96% when compared to the current state-of-the-art swarm intelligence optimization algorithms.