Research progress on weight control and precision of on-chip reconfigurable optical neural networks

On-chip optical neural networks exploit the intrinsic parallelism, high bandwidth, and low propagation loss of photonics to address the throughput and energy limitations of electronic computing. Their practical performance, however, depends on the fidelity with which optical weights are programmed and on the accuracy delivered by the complete optical computing chain. The term “precision” is used inconsistently in the literature, where bit numbers may refer to the number of physical states of one device, the deviation between target and measured weights, or the residual error of a matrix operation. Such metrics describe different objects and cannot be compared directly. A clear distinction is therefore essential for assessing device capability, system-level computational fidelity, and the scalability of photonic neural networks. This review establishes a three-level framework consisting of device-level weight encoding resolution, effective weight-setting bit-width, and output effective computational bit-width, and uses it to organize recent progress in reconfigurable on-chip optical neural networks.

The review first summarizes the weight modulation mechanisms of major on-chip reconfigurable photonic elements. Micro-ring resonators (MRRs) encode weights through resonance detuning, coupling control, or phase-change-material (PCM) integration; Mach–Zehnder interferometers (MZIs) use phase differences and interference to control output intensity; and reconfigurable diffractive metasurfaces adjust the phase response of subwavelength elements through thermo-optic, electro-optic, or nonvolatile phase-change control. PCM-based devices, semiconductor optical amplifiers, multimode-interference elements, three-dimensional waveguide interconnects, and thin-film-lithium-niobate platforms provide additional routes for nonvolatile storage, gain control, fast modulation, and high-density integration.

The review then compares the statistical meanings and error sources of the three precision levels. Encoding resolution is determined by the number of reliably distinguishable physical states and represents the potential precision of an individual weight unit. Effective weight-setting bit-width is derived from target–measured weight deviation or repeated-measurement variation and distinguishes systematic accuracy from random precision. Output effective computational bit-width is obtained from matrix–vector multiplication, dot-product residuals, signal-to-noise ratio, or effective number of bits (ENOB), and incorporates errors from input modulation, weight programming, optical transmission, array coupling, detection, and back-end processing. This distinction shows why a device with many programmable states does not necessarily provide high task-level precision.

Representative developments are reviewed by device family. PCM devices have progressed from three-bit grayscale control to more than seven-bit nonvolatile multilevel programming, while hybrid PCM–electro-optic architectures indicate a path toward effective widths exceeding twelve bits. MRR weight banks have evolved from channel-level feed-forward compensation to feedback calibration, task-driven optimization, full-link monitoring, and proportional–integral–derivative self-calibration. Reported accuracy and precision have consequently advanced from approximately four bits to above nine and eleven bits, respectively, under suitable operating conditions. Parallel bit-slicing further demonstrates that 32-bit system-level reconstruction can be achieved by combining repeated low-precision operations, thereby bypassing the noise limit of a single device. For MZI meshes, the key issue is the propagation of phase, splitter, thermal, and quantization errors through the interference network. Ring-assisted MZI structures, in situ training, complex-valued encoding, and large-scale pre-calibrated arrays improve effective mapping precision and output ENOB. SOA-based photonic tensor processors and other emerging platforms demonstrate that high-resolution current–optical-power calibration, three-dimensional interconnects, multidimensional parallelism, and fast electro-optic materials can complement these approaches.

The field is moving from isolated device characterization toward coordinated suppression of errors across devices, arrays, optical links, and computational architectures. The main remaining challenge is the coupled accumulation of thermal drift, thermal and electrical crosstalk, spectral overlap, loss imbalance, detector noise, and readout error as the array and network depth increase. Calibration and monitoring can improve precision, but they introduce additional detectors, control circuits, latency, and power consumption. Precision must therefore be optimized jointly with throughput, energy efficiency, integration density, refresh speed, long-term stability, and task accuracy. Future research should combine low-loss and highly linear materials with hybrid integration; develop three-dimensional, wavelength-parallel, and multi-channel architectures; and use intelligent calibration, hardware-aware training, and task-driven optimization. Architecture-level methods such as mixed-precision accumulation, parallel bit-slicing, and precision reconstruction are particularly promising because they can raise effective computational fidelity without requiring every physical weight unit to provide an exceptionally large number of stable states. A standardized reporting protocol that specifies the tested object, error statistic, dynamic range, operating conditions, and end-to-end task impact will also be necessary for meaningful comparison. These developments can advance on-chip reconfigurable optical neural networks from isolated demonstrations toward large-scale, robust, and energy-efficient photonic intelligence.