Design of high-precision folding-type time-to-digital converter

This study aims to address key challenges in the design of time-to-digital converters (TDCs) based on field-programmable gate arrays (FPGAs), which are widely used in high-precision time measurement systems. Traditional TDC designs face significant limitations, including difficulty in achieving sub-gate delay resolution, risks associated with long delay chains leading to cross-clock domain issues, and nonlinearity caused by numerous pseudo-thermometer codes. These issues hinder the performance, scalability, and resource efficiency of TDCs in modern applications. To overcome these challenges, this study proposes a novel folding-type tapped delay line (TDL) architecture with multi-chain merging, which incorporates advanced techniques such as dual-sampling and bubble error correction. The primary goal is to enhance measurement resolution and accuracy while minimizing logic resource consumption, thereby providing a more efficient and precise TDC solution for applications requiring high timing precision, such as optical communication, high-energy physics, and quantum computing.

The proposed TDC architecture is implemented on the Xilinx Zynq UltraScale+ MPSoC platform and introduces several innovative design strategies. First, a folding mechanism is applied to reduce the delay chain length by limiting the interpolation range to one-quarter of the clock cycle, significantly decreasing resource utilization. This is achieved through the use of a mixed-mode clock manager to generate four-phase clocks and input/output delay elements (IDELAYE3 and ODELAYE3) to construct a single-cycle delay path. Second, a dual-sampling technique is employed to simultaneously capture the carry and logic outputs of the CARRY8 units, effectively doubling the number of taps and achieving sub-gate delay resolution. Third, a global bubble error correction mechanism is implemented by rearranging the delay line taps and optimizing the ones-counter encoder, thereby mitigating nonlinearity and ensuring accurate decoding of thermometer codes. Additionally, an online calibration module using code density calibration (CDC) is integrated to dynamically compensate for temperature and voltage variations, ensuring stable performance under diverse operating conditions. The overall design is validated through extensive simulations and hardware testing, where key performance metrics such as logical resource consumption, measurement precision, and linearity are evaluated and compared against traditional multi-chain architectures.

The experimental results confirm the effectiveness of the proposed folding-type TDL architecture in improving the performance and resource efficiency of FPGA-TDCs. The folding mechanism reduced the number of delay taps required in the TDL by approximately 74.9%, substantially decreasing hardware resource consumption. Specifically, the lookup table (LUT) usage dropped from 18256 to 5781, a 68.3% reduction, while the flip-flop count decreased from 35329 to 10375, representing a 70.6% reduction. Block RAM (BRAM) usage was reduced from 96 to 68 (29.2% savings), and LUTRAM utilization decreased by 10.8%. To assess linearity, 220 measurements were conducted using the CDC method, which involved generating asynchronous random pulses and analyzing the resulting binary codes. The Least Significant Bit (LSB) resolution was determined to be 1.75 ps. differential nonlinearity (DNL) ranged from -0.68 to 2.70 LSB, while integral nonlinearity (INL) ranged from -14.00 to 18.05 LSB, showing significant linearity improvements over traditional designs. Precision and stability were further evaluated using 51200 repeated measurements of a fixed 100-nanosecond time interval, resulting in a root mean square (RMS) precision of 2.81 ps. The measurement results followed a near-perfect Gaussian distribution, demonstrating high consistency and reliability. Additionally, the system maintained stable RMS precision across a wide range of time intervals (40 to 120 ns), with a peak RMS value of 3.23 ps. These findings highlight the robustness of the proposed architecture, achieving both high precision and excellent linearity while significantly reducing hardware resource consumption.

This study presents a high-resolution, high-precision TDC implemented on the Xilinx Zynq UltraScale+ MPSoC platform using cascaded CARRY8 carry chains. The design introduces innovative folding and dual sampling techniques, achieving substantial improvements in resolution and resource efficiency. To address timing deviations caused by the carry-ahead mechanism, the taps extracted from each CARRY8 unit were carefully rearranged. A nine-stage pipelined ones-counter encoder was employed to enhance encoding speed and mitigate bubble errors, further optimizing system linearity. Compared to FPGA-TDC designs published in the past four years, the proposed TDC demonstrates superior performance in terms of LSB resolution, RMS precision, and logic resource consumption, while maintaining excellent linearity. Despite these achievements, certain limitations remain, such as fluctuations in INL caused by clock skew and process-voltage-temperature variations. Future research could focus on optimizing INL performance, enhancing scalability for more complex applications, and exploring the integration of this architecture into advanced systems, such as quantum computing and high-speed communication networks. Overall, the proposed work provides a practical and efficient approach to high-precision time measurement, offering insights for future TDC development.