Design of CTLE with SS-LMS adaptive equalization algorithm

With the continuous advancement of advanced processes and technologies, in order to ensure the accuracy of data during high-speed transmission, equalizers need to provide higher compensation and lower power consumption to achieve efficient communication. A high-gain and low-power adaptive CTLE (continuous time linear equalizer) was designed on the basis of the 12 nm CMOS (complementary metal-oxide-semiconductor) process, which adopted a two-stage cascade structure to compensate for channel attenuation and improve the quality of the received signal. In addition, the adaptive module used the SS-LMS (sign-sign least mean square) algorithm to accelerate the convergence speed of the tap coefficients. Simulation results show that when the transmission rate is 16 Gbit/s, the equalizer can compensate for a half-bit rate channel attenuation of -15.53 dB, and the equalizer coefficients converge within 16×10⁴ unit interval data. Moreover, after convergence, the received error rate is lower than 10^-12.