On-chip cache design method for cooperative memory compilation and layout

In order to improve the speed of on-chip cache and reduce the area and power consumption, an on-chip cache design method based on cooperative memory compilation and layout was proposed. This method estimated the timing margin of memory array based on its different spatial positions on chip, and then performed memory compilation through exhaustive combination of various configuration parameters such as splitting/merging, size adjustment, threshold replacement and aspect ratio deformation. The best static random-access memory compilation configuration was selected according to the timing margin. This method was integrated with the existing physical design steps into a complete design flow. Experimental results show that this method can reduce the power consumption by about 9.9% and the critical path delay by 7.5%.