Investigation of failure mechanisms and reliability enhancement of fan-out panel-level packaging under temperature cycling

Fan-out panel-level packaging (FOPLP) is regarded as a representative advanced packaging technology due to its high throughput, large exposure area, and low material consumption. However, the high-density integration of multiple materials and complex internal interconnection structures raise significant reliability concerns. In this paper, the reliability of FOPLP under temperature cycling was investigated through a combination of multi-physics finite element simulation and experimental testing, and an optimized packaging design was proposed. First, a multilevel multiphysics coupled finite element model was built based on the package structure. The impact of component coefficients of thermal expansion (CTE) and material matching schemes on package reliability were then analyzed. Subsequently, temperature cycling tests were performed to investigate the failure mechanisms of the package. Finally, the impact of packaging design parameters was evaluated, and an optimized packaging structure was proposed and experimentally validated. The results indicate that the interface between the epoxy molding compound (EMC) above the chip surface and the heat sink is the most vulnerable region, where cracks are likely to initiate and propagate toward the chip, eventually leading to catastrophic failure. By introducing a 1.5-layer interconnect structure to increase the EMC thickness above the chip surface, the stress concentration in reliability-critical regions was significantly reduced, thereby improving the reliability of the FOPLP package.