Thermal Resistance Simulation for CoF Packages

Chip-on-Film (CoF) is a packaging technology that mounts Integrated Circuits (IC) chips directly on a flexible substrate surface. As both power and the number of pins in such packages increase, thermal conditions become more important. In this paper, the thermal resistance of CoF packages is studied using Ansys software to perform finite-element analysis. Because of circuit complexity, two equivalent methods—a length-weighted method and an image-recognition method—are proposed in place of an accurate model to get equivalent thermal conductivity of CoF package devices. In our experiments, the simulated value of thermal resistance based on the length-weighted method was 1.653 K/W, and the value based on the image-recognition method was 1.911 K/W. The real thermal resistance value of the CoF package device is 1.812 K/W. So the error between the real value measured by a tester and the simulated value based on the length-weighted method is 8.8%, and the error between the real value and the simulated value based on the image-recognition method is 5.5%. Hence, both methods can provide effective simulation results, and the image-recognition method is more accurate. In addition, we optimized the CoF package structure. From the simulation results, the drop in thermal resistance after the optimization is obvious.