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With the rapid development in spaceflights and aeroplanes, the demand for low-power and miniaturization techniques has become insistent in modern radar systems. A new framework for low-power modern radar System on a Chip (SoC) based on ASIX core is presented. Pivotal modules and low-power design flows are described in detail. The dynamic clock-distribution mechanism of the power management module and the influence of the chip power are both stressed. This design adopts the SMIC 0.18- μm 1P6M Salicide CMOS process, the area is 7.825 mm × 7.820 mm, there are approximately 2 million gates and the frequency is 100 MHz. The results show that the modern radar SoC passes the test on modern radar application system and meets the design requirements. The chip incurs power savings of 42.79% during the fore-end phase and 12.77% during the back-end phase. The total power is less than 350 mW for a 100-MHz operating environment.


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Design of Low-Power Modern Radar SoC Based on ASIX

Show Author's information Bing YangZongguang Yu( )Jinghe Wei
Schoolol of Internet of Things Engineering, Jiangnan University, Wuxi 214122, China
China Electronics Technology Group Corporation No.58 Research Institute, Wuxi 214035, China

Abstract

With the rapid development in spaceflights and aeroplanes, the demand for low-power and miniaturization techniques has become insistent in modern radar systems. A new framework for low-power modern radar System on a Chip (SoC) based on ASIX core is presented. Pivotal modules and low-power design flows are described in detail. The dynamic clock-distribution mechanism of the power management module and the influence of the chip power are both stressed. This design adopts the SMIC 0.18- μm 1P6M Salicide CMOS process, the area is 7.825 mm × 7.820 mm, there are approximately 2 million gates and the frequency is 100 MHz. The results show that the modern radar SoC passes the test on modern radar application system and meets the design requirements. The chip incurs power savings of 42.79% during the fore-end phase and 12.77% during the back-end phase. The total power is less than 350 mW for a 100-MHz operating environment.

Keywords: ASIX core, System on a Chip (SoC), low power, system level, circuit level, logic level, physical level, modern radar

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Publication history

Received: 18 February 2014
Revised: 24 February 2014
Accepted: 04 March 2014
Published: 15 April 2014
Issue date: April 2014

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© The author(s) 2014

Acknowledgements

This work was funded by the "333 Engineering" Assistance Project of Jiangsu Province, China (No. BRA2011115).

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