Optimization and Evaluation of Sputtering Barrier/Seed Layer in Through Silicon Via for 3-D Integration

The barrier/seed layer is a key issue in Through Silicon Via (TSV) technology for 3-D integration. Sputtering is an important deposition method for via metallization in semiconductor process. However, due to the limitation of sputtering and a "scallop" profile inside vias, poor step coverage of the barrier/seed layer always occurs in the via metallization process. In this paper, the effects of several sputter parameters (DC power, Ar pressure, deposition time, and substrate temperature) on thin film coverage for TSV applications are investigated. Robust TSVs with aspect ratio 5∶1 were obtained with optimized magnetron sputter parameters. In addition, the influences of different sputter parameters are compared and the conclusion could be used as a guideline to select appropriate parameter sets.