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Reverse Programmed SONOS Memory Technique for 0.18 μm Embedded Utilization

Liyang PAN( ), Lei SUN, Dong WU, John CHEN†, Jun XU, Jun ZHU
Institute of Microelectronics, Tsinghua University, Beijing 100084, China
Semiconductor Manufacture International Corporation, Shanghai 201203, China
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Abstract

A 4 Mb embedded silicon-oxide-nitride-oxide-silicon (SONOS) memory was developed with a 0.18 µm CMOS logic compatible technology. A reverse programming array architecture was proposed to reduce the chip area, enhance the operating window, and increase the read speed. The charge distribution was analyzed to optimize the programming and erase conditions considering both the operating speed and the endurance performance. The final test chip has a good endurance of 105 cycles and a data retention time of at least 10 years.

Keywords

flash memorysilicon-oxide-nitride-oxide-silicon (SONOS)charge distributionenduranceretention

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Tsinghua Science and Technology
Volume 12 Issue 6,
December 2007
Pages 741-746
DOI: 10.1016/S1007-0214(07)70183-9

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Cite this article:
PAN L, SUN L, WU D, et al. Reverse Programmed SONOS Memory Technique for 0.18 μm Embedded Utilization. Tsinghua Science and Technology, 2007, 12(6): 741-746. https://doi.org/10.1016/S1007-0214(07)70183-9

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Received: 05 March 2007
Revised: 29 June 2007
Published: 01 December 2007
© Tsinghua University Press 2007