Wafer-scale carbon-based CMOS PDK compatible with silicon-based VLSI design flow

Carbon nanotube field-effect transistors (CNTFETs) are increasingly recognized as a viable option for creating high-performance, low-power, and densely integrated circuits (ICs). Advancements in carbon-based electronics, encompassing materials and device technology, have enabled the fabrication of circuits with over 1,000 gates, marking carbon-based integrated circuit design as a burgeoning field of research. A critical challenge in the realm of carbon-based very large-scale integration (VLSI) is the lack of suitable automated design methodologies and infrastructure platforms. In this study, we present the development of a wafer-scale 3 µm carbon-based CMOS PDK compatible with silicon-based EDA tools and VLSI circuit design flow. The proposed 3 µm-CNTFETs-PDK features a contacted gate pitch (CGP) of 21 µm, a gate density of 128 gates/mm², and a transistor density of 554 transistors/mm², with an intrinsic gate delay around 134 ns. Validation of the 3 µm-CNTFETs-PDK was achieved through the successful design and tape-out of 153 standard cells and 333-stage ring oscillator circuits. Leveraging the carbon-based PDK and a silicon-based design platform, we successfully implemented a complete 64-bit SRAM circuit system for the first time, exhibiting timing, power, and area characteristics of clock@10K Hz, 122.1 uW, 3795×2810 µm². This research confirms that carbon-based IC design can be compatible with existing EDA tools and silicon-based VLSI design flow, thereby laying the groundwork for future carbon-based VLSI advancements.