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Brain-inspired neuromorphic computing is expected for breaking through the bottleneck of the computer of conventional von Neumann architecture. To this end, the first step is to mimic functions of biological neurons and synapses by electronic devices. In this paper, synaptic transistors were fabricated by using carbon nanotube (CNT) thin films and interface charge trapping effects were confirmed to dominate the weight update of the synaptic transistors. Large synaptic weight update was realized due to the high sensitivity of the CNTs to the trapped charges in vicinity. Basic synaptic functions including inhibitory post-synaptic current (IPSC), excitatory post-synaptic current (EPSC), spike-timing-dependent plasticity (STDP), and paired-pulse facilitation (PPF) were mimicked. Large dynamic range of STDP (> 2, 180) and low power consumption per spike (~ 0.7 pJ) were achieved. By taking advantage of the long retention time of the trapped charges and uniform device-to-device performance, long-term image memory behavior of neural network was successfully imitated in a CNT synaptic transistor array.


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Charge trap-based carbon nanotube transistor for synaptic function mimicking

Show Author's information Jie Zhao1,2Fang Liu1,2Qi Huang1,2Tongkang Lu1,2Meiqi Xi1,2Lianmao Peng1,2,3Xuelei Liang1,2,3,4( )
Center for Carbon-Based Electronics Peking University Beijing 100871 China
Key Laboratory for the Physics and Chemistry of Nanodevices Department of Electronics Peking University Beijing 100871 China
Shanxi Institute for Carbon-Based Thin Film Electronics Peking University (SICTFE-PKU) Taiyuan 030012 China
Taiyuan Laboratory for Carbon-Based Thin Film Electronics Taiyuan 030012 China

Abstract

Brain-inspired neuromorphic computing is expected for breaking through the bottleneck of the computer of conventional von Neumann architecture. To this end, the first step is to mimic functions of biological neurons and synapses by electronic devices. In this paper, synaptic transistors were fabricated by using carbon nanotube (CNT) thin films and interface charge trapping effects were confirmed to dominate the weight update of the synaptic transistors. Large synaptic weight update was realized due to the high sensitivity of the CNTs to the trapped charges in vicinity. Basic synaptic functions including inhibitory post-synaptic current (IPSC), excitatory post-synaptic current (EPSC), spike-timing-dependent plasticity (STDP), and paired-pulse facilitation (PPF) were mimicked. Large dynamic range of STDP (> 2, 180) and low power consumption per spike (~ 0.7 pJ) were achieved. By taking advantage of the long retention time of the trapped charges and uniform device-to-device performance, long-term image memory behavior of neural network was successfully imitated in a CNT synaptic transistor array.

Keywords: carbon nanotube, charge trap, synaptic transistor, long-term memory

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Publication history
Copyright
Acknowledgements

Publication history

Received: 13 March 2021
Revised: 02 May 2021
Accepted: 20 May 2021
Published: 13 July 2021
Issue date: November 2021

Copyright

© Tsinghua University Press and Springer-Verlag GmbH Germany, part of Springer Nature 2021

Acknowledgements

Acknowledgements

This work was supported by the National Key Research and Development Program (No. 2016YFA0201902), the National Natural Science Foundation of China (No. 51991341), and the Open Research Fund of Key Laboratory of Space Utilization, and Chinese Academy of Sciences (No. LSU-KFJJ-2020-06).

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