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Research Article

Tunnel junctions in a III–V nanowire by surface engineering

Salman Nadar1, Chloé Rolland1, Jean-François Lampin1, Xavier Wallart1, Philippe Caroff1,2( ), Renaud Leturcq1,3( )
ISEN DepartmentInstitute of Electronics Microelectronics and NanotechnologyCNRS-UMR 8520Avenue PoincaréCS 6006959652Villeneuve d'Ascq Cedex, France
Department of Electronic Materials EngineeringResearch School of Physics and EngineeringThe Australian National UniversityCanberraACT0200Australia
Département Science et Analyse des MatériauxCentre de Recherche Public-Gabriel Lippmann41 rue du BrillL-4422BelvauxLuxembourg
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Abstract

We demonstrate a simple way of fabricating high performance tunnel devices from p-doped InAs nanowires by tailoring the n-doped surface accumulation layer inherent to InAs surfaces. By using appropriate ammonium sulfide based surface passivation before metallization without any further thermal treatment, we demonstrate characteristics of tunnel p-n junctions, namely Esaki and backward diodes, with figures of merit better than previously published for InAs homojunctions. The further optimization of both the surface doping, in a quantitative way, and the device geometry allows us to demonstrate that these nanowire-based technologically-simple diodes have promising direct current characteristics for integrated high frequency detection or generation.

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Nano Research
Pages 980-989

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Cite this article:
Nadar S, Rolland C, Lampin J-F, et al. Tunnel junctions in a III–V nanowire by surface engineering. Nano Research, 2015, 8(3): 980-989. https://doi.org/10.1007/s12274-014-0579-8

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Received: 03 July 2014
Revised: 03 September 2014
Accepted: 06 September 2014
Published: 10 October 2014
© Tsinghua University Press and Springer-Verlag Berlin Heidelberg 2014