Facile Fabrication of All-SWNT Field-Effect Transistors
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Field-effect transistors (FETs) have been fabricated using as-grown single-walled carbon nanotubes (SWNTs) for the channel as well as both source and drain electrodes. The underlying Si substrate was employed as the back-gate electrode. Fabrication consisted of patterned catalyst deposition by surface modification followed by dip-coating and synthesis of SWNTs by alcohol chemical vapor deposition (CVD). The electrodes and channel were grown simultaneously in one CVD process. The resulting FETs exhibited excellent performance, with an ION/IOFF ratio of 106 and a maximum ON-state current (ION) exceeding 13 μA. The large ION is attributed to SWNT bundles connecting the SWNT channel with the SWNT electrodes. Bundling creates a large contact area, which results in a small contact resistance despite the presence of Schottky barriers at metallic–semiconducting interfaces. The approach described here demonstrates a significant step toward the realization of metal-free electronics.
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Facile Fabrication of All-SWNT Field-Effect Transistors
)
Abstract
Field-effect transistors (FETs) have been fabricated using as-grown single-walled carbon nanotubes (SWNTs) for the channel as well as both source and drain electrodes. The underlying Si substrate was employed as the back-gate electrode. Fabrication consisted of patterned catalyst deposition by surface modification followed by dip-coating and synthesis of SWNTs by alcohol chemical vapor deposition (CVD). The electrodes and channel were grown simultaneously in one CVD process. The resulting FETs exhibited excellent performance, with an ION/IOFF ratio of 106 and a maximum ON-state current (ION) exceeding 13 μA. The large ION is attributed to SWNT bundles connecting the SWNT channel with the SWNT electrodes. Bundling creates a large contact area, which results in a small contact resistance despite the presence of Schottky barriers at metallic–semiconducting interfaces. The approach described here demonstrates a significant step toward the realization of metal-free electronics.
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Acknowledgements
Part of this work was financially supported by Grantsin-Aid for Scientific Research (Nos. 19054003 and 22226006), New Energy and Industrial Technology Development Organization (NEDO) (Japan), "Development of Nanoelectronic Device Technology" of NEDO, and Global COE Program "Global Center for Excellence for Mechanical Systems Innovation". One of the authors (SA) was financially supported by a JSPS Fellowship (No. 21-1436). This work is also supported by the Very-Large-Scale Integration (VLSI) Design and Education Center (VDEC), The University of Tokyo, in collaboration with Cadence Corporation.
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