Development of Ultra-High Density Silicon Nanowire Arrays for Electronics Applications

This article reviews our recent progress on ultra-high density nanowires (NWs) array-based electronics. The superlattice nanowire pattern transfer (SNAP) method is utilized to produce aligned, ultra-high density Si NW arrays. We first cover processing and materials issues related to achieving bulk-like conductivity characteristics from 10–20 nm wide Si NWs. We then discuss Si NW-based field-effect transistors (FETs). These NWs & NW FETs provide terrific building blocks for various electronic circuits with applications to memory, energy conversion, fundamental physics, logic, and others. We focus our discussion on complementary symmetry NW logic circuitry, since that provides the most demanding metrics for guiding nanofabrication. Issues such as controlling the density and spatial distribution of both p- and n-type dopants within NW arrays are discussed, as are general methods for achieving Ohmic contacts to both p- and n-type NWs. These various materials and nanofabrication advances are brought together to demonstrate energy efficient, complementary symmetry NW logic circuits.