@article{Ran2026, 
author = {Jingwen Ran and Fan Zhang and Chong Chen and Tianyu Guan and Bo Wen and Yijun Guo and Xiuyu Yao and Anyu Sun and Yuanliu Chen},
title = {A Multiphysics-Coupled 3D Visualization Model for Controlling Ultrafast Laser-Induced Micro-Hole Morphology on Monocrystalline Silicon},
year = {2026},
journal = {Nanomanufacturing and Metrology},
volume = {9},
number = {2},
pages = {12},
keywords = {Femtosecond laser ablation, 3D visualization model, Multiphysics modeling, Micro-hole morphology control, Monocrystalline silicon},
url = {https://www.sciopen.com/article/10.1007/s41871-026-00293-0},
doi = {10.1007/s41871-026-00293-0},
abstract = {The demand for micro/nano-fabrication is rapidly increasing with the continuous miniaturization of industrial devices. Ultrafast laser technology has emerged as a promising solution, offering high peak power, minimal heat-affected zones, and nonlinear processing capabilities. However, the complex interplay between laser parameters and resulting micro/nanostructures necessitates precise modeling for intuitive morphology control and effective process optimization. Therefore, this study proposes a novel multiphysics-coupled 3D visualization model that integrates ablation dynamics, phase transition behavior, and dynamic mesh technology. The model establishes a cross-scale mapping between surface node motion and staged ablation rates by coupling ablation and phase transition dynamics with dynamic meshing to reveal the mechanisms of micro-hole formation and quantitatively link feature size to single-pulse laser parameters. Experimental validation based on femtosecond laser pulses with varying energies showed high consistency between simulations and measurements in ultrafast laser-induced micro-hole morphology control, with prediction errors of less than 5.3% and 7.8% for micro-hole diameter and depth, respectively, achieved without prior optimization. This study provides meaningful insights into ultrafast laser-induced microstructure control and serves as a practical reference for semiconductor chip design.}
}