@article{LU2025, 
author = {Lu LU and Yuanfei WANG and Zhihong LIANG and Siliang SUO},
title = {Design and Optimization of Fast Fourier Transform Algorithm Based on Ascend NPU},
year = {2025},
journal = {Journal of South China University of Technology (Natural Science Edition)},
volume = {53},
number = {11},
pages = {9-17},
keywords = {fast Fourier transform, Ascend NPU, heterogeneous computing, high-performance computing},
url = {https://www.sciopen.com/article/10.12141/j.issn.1000-565X.240524},
doi = {10.12141/j.issn.1000-565X.240524},
abstract = {As a fundamental algorithm in scientific computing and signal processing, fast Fourier transform (FFT) has been widely applied to such fields as digital signal processing, image processing, deep learning. With the growth of data scale and the increasing demand for processing power, optimizing FFT algorithms on emerging hardware platforms has become particularly crucial. This paper conducts an in-depth analysis of the architectural characteristics of Ascend NPU and their impacts on FFT algorithm optimization. Based on the matrix-computation-based Stockham FFT algorithm, a series of innovative optimization strategies are proposed: (1) A heuristic radix selection algorithm is designed to provide effective radix sequence combinations for different input sizes; (2) An efficient computation flow for single-iteration FFT without real-imaginary separation is developed, significantly reducing the global memory access overhead; (3) An on-chip cache-based data reading optimization strategy is proposed, greatly improving data access speed; (4) A data layout optimization method for multiple iterations is designed, effectively enhancing overall memory access efficiency. Experimental results on Ascend Atlas 800 platform equipped with Ascend 910 AI processor demonstrate that the proposed optimization strategies achieve an average speedup of 4.61 compared to non-optimized implementations. Independent performance analysis and validation of each optimization strategy demonstrate that the individual average speedup ratio ranges from 1.42 to 3.52. This research provides a technical references for implementing efficient FFT algorithms on emerging NPU architectures.}
}