@article{Huang2026, 
author = {Mengting Huang and Shuangquan Qu and Yiming Ding and Binbin Zhang and Shibo Wang and Xiaolong Xu and Yeliang Wang},
title = {Mitigating Fermi-level pinning in 2D transistors via reactive phase-transformed contacts},
year = {2026},
journal = {Nano Research},
keywords = {contact, Fermi-level pinning, two-dimensional (2D) semiconductor devices, PdTe2},
url = {https://www.sciopen.com/article/10.26599/NR.2026.94908890},
doi = {10.26599/NR.2026.94908890},
abstract = {The integration of high-performance two-dimensional (2D) semiconductor devices is fundamentally bottlenecked by severe Fermi-level pinning (FLP) at the metal-semiconductor interface. Direct deposition of high-work-function, high-melting-point metals typically inflicts structural damage on the 2D lattice, generating interfacial defects that strongly pin the Fermi level. Here, we report a damage-free metallization strategy utilizing low-temperature phase engineering to achieve highly conductive, weakly pinned contacts. We employ a low-energy evaporation of tellurium (Te) as a non-destructive buffer layer, which effectively shields the underlying 2D channel during the subsequent deposition of palladium (Pd). Through a precisely controlled low-temperature annealing process, the Te and Pd layers undergo a solid-state reaction, transforming into a highly conductive, high-work-function metallic PdTe2 phase. We demonstrate that PdTe2-contacted MoTe2 field-effect transistors (FETs) exhibit significantly enhanced electrical performance compared to those with directly deposited Pd or unannealed Te/Pd contacts. Furthermore, applying this strategy to WSe2 FETs shifts the transport from a strongly pinned n-type behavior—characteristic of direct Pd contacts—to a weakly pinned ambipolar characteristic with superior electrical properties. Crucially, the low thermal budget of this phase-transformation process offers a scalable pathway for integrating pristine, high-performance 2D electronics.}
}