@article{WEI2010, 
author = {Qi WEI and Dandan HAN and Huazhong YANG},
title = {Dual-Mode Low Power Pipelined ADC with Pre-charged Switched Operational Amplifier},
year = {2010},
journal = {Tsinghua Science and Technology},
volume = {15},
number = {2},
pages = {221-227},
keywords = {analog-to-digital converter, pipeline, switched operational amplifier},
url = {https://www.sciopen.com/article/10.1016/S1007-0214(10)70054-7},
doi = {10.1016/S1007-0214(10)70054-7},
abstract = {This paper describes a 12-bit 40-MS/s and 8-bit 80-MS/s dual-mode low power pipelined analog-to-digital converter (ADC). An improved multiplying digital-to-analog converter is used to provide the dual-mode operation. A pre-charged fast power-on switched operational amplifier is used to reduce the power consumption of the pipelined ADC to 28.98 mW/32.74 mW at 40 MHz/80 MHz sampling rates. The ADC was designed in a 1.8-V 1P6M 0.18-μm CMOS process. Simulations indicate that the ADC exhibits a spurious free dynamic range of 90.24 dB/58.33 dB and signal-to-noise-and-distortion ratio of 73.81 dB/47.85 dB at 40 MHz/80 MHz sampling frequencies for a 19-MHz input sinusoidal signal.}
}