@article{YU2026, 
author = {Zhiguo YU and Muhao CHEN and Xiaoyu ZHONG and Qiyan LU and Wenzhuo LI and Xiaofeng GU},
title = {A reconfigurable SAR ADC with pseudo-multiple sampling and calibration for CMOS image sensors},
year = {2026},
journal = {Journal of Measurement Science and Instrumentation},
volume = {17},
number = {1},
pages = {114-124},
keywords = {CMOS image sensor (CIS), reconfigurable analog-to-digital (A/D) converter (ADC), successive approximation register (SAR), error calibration, pseudo-multiple sampling (PMS)},
url = {https://www.sciopen.com/article/10.62756/jmsi.1674-8042.2026009},
doi = {10.62756/jmsi.1674-8042.2026009},
abstract = {This paper presents a resolution reconfigurable two-step successive approximation register analog-to-digital (A/D) converter (ADC) with the pseudo-multiple sampling (PMS) and gain error calibration method for CMOS image sensors. The proposed ADC can be configured with 10-bit, 11-bit and 12-bit by adjusting the number of 10-bit A/D conversions, thereby satisfying various demands in different situations. The PMS method enables the attainment of high-resolution ADC results by summing the conversion outputs of several low-resolution ADCs, thereby reducing the number of unit capacitors and the area of the capacitor array. A compensation technique is proposed to expand the quantization range and improve the effective resolution of the proposed ADC. A calibration method suitable for bottom-plate sampling is proposed, which reduces the gain error between reference voltages. Simulated in a 55 nm process, the proposed ADC in the 12-bit mode achieves a differential nonlinearity of +0.47/−0.50 least significant bit (LSB) and an integral nonlinearity of +0.75/−0.84 LSB at a sampling frequency of 3.497×105 per second with the calibration. The effective number of bits reaches 11.63 bits. The area occupied by a single ADC column is 39.5 µm×119.2 µm and the power consumption is 62.8 µW.}
}