@article{YU2026, 
author = {Zongyuan YU and Lunyao WANG and Zhufei CHU and Yinshui XIA},
title = {Area optimization of logic circuits in HDL-level using approximate computing},
year = {2026},
journal = {Journal of Beijing University of Aeronautics and Astronautics},
volume = {52},
number = {3},
pages = {908-916},
keywords = {approximate computing, area optimization, HDL-level optimization, Verilog HDL, logic synthesis},
url = {https://www.sciopen.com/article/10.13700/j.bh.1001-5965.2023.0838},
doi = {10.13700/j.bh.1001-5965.2023.0838},
abstract = {Given that the current area optimization at the hardware description language (HDL) level using approximate computing techniques is unable to effectively utilize the optimization space provided by quality-of-result (QoR) constraints, an approximate optimization algorithm for arithmetic circuits is proposed. This algorithm includes the selection mechanism of the proposed approximate operations, internal signal bit-width reduction, arithmetic operator replacement, and approximate arithmetic cell circuits calling. The proposed algorithm is programmed in C and the circuit area is estimated by Design Compiler. The experimental results show that under the constraint of QoR, compared with the non-approximate optimization result, the average area saving is 55.2%. The suggested approach can further increase the average area save by 24.9% when compared to the reported approximate strategy.}
}