@article{Yao2025, 
author = {Lian Yao and Jigang Wu and Peng Liu},
title = {A Research on Logic Synthesis for Dual-domain Memristive Circuits},
year = {2025},
journal = {Journal of Guangdong University of Technology},
volume = {42},
number = {6},
pages = {27-33},
keywords = {memristive logic, logic synthesis, optimization for graph topology},
url = {https://www.sciopen.com/article/10.12052/gdutxb.250162},
doi = {10.12052/gdutxb.250162},
abstract = {Memristors, originally exploited for nonvolatile storage, are now intensively investigated as logic primitives capable of in-memory computing, offering a promising solution to break the “memory wall”. However, when targeting the design of large and complex circuits, existing synthesis flows restricted to a single memristive logic lack the flexibility, leading to results that the performance metrics of circuits fall short of design targets. In this work, a dual-domain synthesis framework is proposed that synergistically combines memristor-based implication (IMP) logic and not-implication (N-IMP) primitives. By systematically analyzing their mapping and scheduling characteristics on circuit netlists, three cooperative strategies are introduced during the process of technology-independent optimization: optimization for rewriting the minimal-substructure, disjunctive/conjunctive duality selection for multiplexers, and collective refactoring of multi-fan-out clusters. The proposed methods achieve high-performance graph topology transformation and scheduling. Experimental results show that, compared with ABC tool, the proposed methods achieve the reduction of number of nodes after mapping by 17.32%. Furthermore, the proposed methods achieve the improvement in area overhead by 61.5% during the process of scheduling, when compared with the state-of-the-art work (AND-OR) .}
}