@article{XU2024, 
author = {Jinwei XU and Qinglin WANG and Yalin LI and Jingfei JIANG and Lei GAO and Rongchun LI and Dongsheng LI},
title = {Parallel optimization of convolution algorithm on multi-core DSP},
year = {2024},
journal = {Journal of National University of Defense Technology},
volume = {46},
number = {1},
pages = {103-112},
keywords = {multi-core DSP, CNNs, convolutional algorithms, parallel optimization},
url = {https://www.sciopen.com/article/10.11887/j.cn.202401011},
doi = {10.11887/j.cn.202401011},
abstract = {According to the characteristics of the heterogeneous multi-core DSP (digital signal processing) chip independently developed by National University of Defense Technology and the characteristics of the convolution algorithm, a high-performance multi-core parallel convolution implementation scheme for multi-core DSP architecture was proposed. A feature graph level multi-core parallel scheme is proposed for 1 × 1 convolution. For convolutions with kernels larger than 1, a window level multi-core parallel optimization design was proposed, and an element-wise vectorization based intra-core parallel optimization implementation was proposed. The experimental results show that the proposed parallel optimization method can reach a maximum single core computing efficiency of 64.95%. When the bandwidth is limited, the parallel expansion efficiency of multi-core can still reach 48.36% ~ 88.52%. Compared with E5-2640 CPU, the execution performance on the typical network ResNet50 achieves 5.39x performance acceleration.}
}